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AT16646F-25YC Datasheet

  • AT16646F-25YC

  • AT16646 Fast Logic 16-Bit Tri-State Register

  • 6頁

  • ATMEL   ATMEL

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AT16646
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Fastest Propagation Speeds in the Industry T
PD (F grade)
= 2.5 ns, T
PD (G grade)
= 2.0 ns
Maximum derating for capacitive loads 1.5ns/100 pF (F grade) and 1.1ns/100 pF
(G grade)
Very low ground bounce < 0.6 V @ V
CC
=5.00 V, T
a
=25擄C
Typical output skew
鈮?.25ns
鈩?/div>
Bus Hold circuitry to retain last active state during Tri-State鈩?/div>
Available in SSOP and TSSOP packages
Description
Atmel鈥檚 AT16646 devices are 16-bit high speed, low power Tri-statable D type
registers, ideal for use in systems requiring both transparent and registered mode
functions. They are organized as two separate 8-bit bus transceivers. Data flow is
bi-directional, and can be controlled for multiplexed transmission between A bus and
B bus either directly or from the D registers by use of the direction control pin (xDir),
output enable (xOE), and select lines (xSAB and xSBA). Storage of data on the A bus
and B bus is controlled by the output pins. They have very low ground bounce and
excellent input noise rejection, giving the user stable signals in a high speed
environment. The Bus Hold feature eliminates the need for pull-up or pull-down
resistors and retains the last active state during a Tri-State event.
AT16646
Fast Logic
鈩?/div>
16-Bit
Tri-State
鈩?/div>
Register
AT16646F
AT16646G
Functional Block Diagram
Pin Configurations
1DIR
SSOP/TSSOP
1SAB
1A1
VCC
1A4
GND
1A7
2A1
2A3
2A4
2A6
2A7
GND
2CLKAB
1CLKAB
GND
1A2
1A3
1A5
1A6
1A8
2A2
GND
2A5
VCC
2A8
2SAB
2DIR
1
3
5
7
9
11
13
15
17
19
21
23
25
27
2
4
6
8
10
12
14
16
18
20
22
24
26
28
56
54
52
50
48
46
44
42
40
38
36
34
32
30
55
53
51
49
47
45
43
41
39
37
35
33
31
29
1CLKBA
GND
1B2
1B3
1B5
1B6
1B8
2B2
GND
2B5
VCC
2B8
2SBA
2OE
1OE
1SBA
1B1
VCC
1B4
GND
1B7
2B1
2B3
2B4
2B6
2B7
GND
2CLKBA
Pin Names
xDir, xOE
xCLKAB,xCLKBA
xSAB, xSBA
xA蠂
xB蠂
Descriptions
Output Enable Inputs
Clock Pulse Inputs
Output Data Source Select Inputs
Data Register A Inputs
Data Register B Outputs
Data Register B Inputs
Data Register A Outputs
Top View
0757B
5-21

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