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ASM5P23S04AG-1H-08-SR Datasheet

  • ASM5P23S04AG-1H-08-SR

  • 3.3V SpreadTrak Zero Delay Buffer

  • 348.13KB

  • 15頁(yè)

  • ALSC

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September 2005
rev 1.3
3.3V 鈥楽preadTrak鈥?Zero Delay Buffer
Features
Zero input - output propagation delay, adjustable
by capacitive load on FBK input.
Multiple configurations - Refer 鈥淎SM5P23S04A
Configurations Table鈥?
Input frequency range: 15MHz to 133MHz
Multiple low-skew outputs.
Output-output skew less than 200pS.
Device-device skew less than 500pS.
Two banks of two outputs each.
Less than 200pS Cycle-to-cycle jitter
(-1, -1H, -2, -2H).
Available in space saving, 8 pin 150-mil SOIC
package.
3.3V operation.
Advanced 0.35碌 CMOS technology.
Industrial temperature available.
鈥楽preadTrak鈥?
The
ASM5P23S04A
(Refer
is
ASM5P23S04A
the REF pin. The PLL feedback is required to be driven to
FBK pin, and can be obtained from one of the outputs. The
input-to-output propagation delay is guaranteed to be less
than 250pS, and the output-to-output skew is guaranteed to
be less than 200pS.
The ASM5P23S04A has two banks of two outputs each.
Multiple ASM5P23S04A devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
500pS.
available
in
two
different
configurations
鈥淎SM5P23S04A
Configurations
Table). The ASM5P23S04A-1 is the base part, where the
output frequencies equal the reference if there is no
counter in the feedback path. The ASM5P23S04A-1H is
the high-drive version of the -1 and the rise and fall times
on this device are much faster.
Functional Description
ASM5P23S04A is a versatile, 3.3V zero-delay buffer
designed
to
distribute
high-speed
clocks
in
PC,
workstation, datacom, telecom and other high-performance
applications. It is available in a 8 pin package. The part has
an on-chip PLL, which locks to an input clock, presented on
The ASM5P23S04A-2 allows the user to obtain REF and
1/2X or 2X frequencies on each output bank. The exact
configuration and output frequencies depend on which
output drives the feedback pin.
Block Diagram
FBK
CLKA1
REF
PLL
CLKA2
/2
Extra Divider (-2)
CLKB1
CLKB2
Alliance Semiconductor
2575 Augustine Drive
鈥?/div>
Santa Clara, CA
鈥?/div>
Tel: 408.855.4900
鈥?/div>
Fax: 408.855.4999
鈥?/div>
www.alsc.com
Notice: The information in this document is subject to change without notice.

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