音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

ASM5I9774AG-52-ET Datasheet

  • ASM5I9774AG-52-ET

  • 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer

  • 12頁

  • ALSC

掃碼查看芯片數(shù)據(jù)手冊

上傳產品規(guī)格書

PDF預覽

June 2005
rev 0.3
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
Output frequency range: 8.3MHz to 125MHz
Input frequency range: 4.2MHz to 62.5MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
14 Clock outputs: Drive up to 28 clock lines
1 Feedback clock output
2 LVCMOS reference clock inputs
150 pS max output-output skew
PLL bypass mode
鈥楽preadTrak鈥?/div>
Output enable/disable
Pin compatible with MPC9774 and CY29774AI.
Industrial temperature range: 鈥?0擄C to +85擄C
52Pin 1.0mm TQFP package
RoHS Compliance
ASM5I9774A
The ASM5I9774A features two reference clock inputs and
provides 14 outputs partitioned in 3 banks of 5, 5, and 4
outputs. Bank A and Bank B divide the VCO output by 4 or
8 while Bank C divides by 8 or 12 per SEL(A:C) settings,
see Functional Table. These dividers allow output to input
ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each
LVCMOS compatible output can drive 50鈩?series or
parallel
terminated
transmission
lines.
For
series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:28.
The PLL is ensured stable given that the VCO is configured
to run between 200 MHz to 500 MHz. This allows a wide
range of output frequencies from 8.3 MHz to 125 MHz. For
normal operation, the external feedback input, FB_IN, is
connected to the feedback output, FB_OUT. The internal
VCO is running at multiples of the input reference clock set
by the feedback divider, see Frequency Table.
Functional Description
The ASM5I9774A is a low-voltage high-performance
125MHz PLL-based zero delay buffer designed for high-
speed clock distribution applications.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
Block Diagram
VCO_SEL
PLL_EN
TCLK_SEL
TCLK0
TCLK1
FB_IN
SELA
+2/+4
CLK
STOP
+2
PLL
200-
500MHZ
+2/+4
+4
CLK
STOP
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QB4
SELB
+4/+6
SELC
CLK_STP#
CLK
STOP
QC0
QC1
QC2
QC3
FB_OUT
+4/+6/+8/+12
FB_SEL(1.0)
MR#/OE
Alliance Semiconductor
2575, Augustine Drive
鈥?/div>
Santa Clara, CA
鈥?/div>
Tel: 408.855.4900
鈥?/div>
Fax: 408.855.4999
鈥?/div>
www.alsc.com
Notice: The information in this document is subject to change without notice.

ASM5I9774AG-52-ET相關型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務：
賣家服務：
技術客服：

0571-85317607

網站技術支持

13606545031

客服在線時間周一至周五
9:00-17:30

關注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務的動力！意見一經采納，將有感恩紅包奉上哦！