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Output enable/disable
Pin-compatible with MPC9351 and CY29351.
Industrial temperature range: 鈥?0擄C to +85擄C
32-pin 1.0mm TQFP & LQFP Package.
ASM5I9351
The ASM5I9351 features LVPECL and LVCMOS reference
clock inputs and provides 9 outputs partitioned in 4 banks
of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by
2 or 4 while the other banks divide by 4 or 8 per SEL(A:D)
settings, see Table.2. These dividers allow output to input
ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS
compatible output can drive 50鈩?series or parallel
terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured
to run between 200 MHz to 500 MHz. This allows a wide
range of output frequencies from 25 MHz to 200 MHz. For
normal operation, the external feedback input, FB_IN, is
connected to one of the outputs. The internal VCO is
running at multiples of the input reference clock set by the
feedback divider, see the Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
Functional Description
The ASM5I9351 is a low
voltage high performance
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
200MHz PLL-based zero delay buffer designed for high
speed clock distribution applications.
Alliance Semiconductor
2575, Augustine Drive
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Santa Clara, CA
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Tel: 408.855.4900
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Fax: 408.855.4999
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www.alsc.com
Notice: The information in this document is subject to change without notice.
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