鈥楽preadTrak鈥?/div>
Output enable/disable
Pin-compatible with MPC9350 and CY29350.
Industrial temperature range: 鈥?0擄C to +85擄C
32-pin 1.0mm TQFP & LQFP Packages
ASM5I9350
The ASM5I9350 features Xtal and LVCMOS reference
clock inputs and provides nine outputs partitioned in four
banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO
output by 2 or 4 while the other banks divide by 4 or 8 per
SEL(A:D) settings, see Table 2. These dividers allow
output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each
LVCMOS compatible output can drive 50鈩?series or
parallel
terminated
transmission
lines.
For
series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured
to run between 200MHz to 500MHz. This allows a wide
range of output frequencies from 25MHz to 200MHz. The
internal VCO is running at multiples of the input reference
clock set by the feedback divider, see Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
Functional Description
The
ASM5I9350
is
a
low-voltage
high-performance
does not apply.
200MHz PLL-based clock driver designed for high speed
clock distribution applications.
Alliance Semiconductor
2575, Augustine Drive
鈥?/div>
Santa Clara, CA
鈥?/div>
Tel: 408.855.4900
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Fax: 408.855.4999
鈥?/div>
www.alsc.com
Notice: The information in this document is subject to change without notice.
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