鈥?/div>
Low skew; low jitter PLL clock driver.
1 to 10 differential clock distribution (SSTL_2).
Feedback pins for input to output synchronization.
PDB for power management.
Spread spectrum tolerant inputs.
Auto-PD when input signal removed.
Choice of static phase offset for easy board tuning:
鈥?-XXX = device pattern number for options listed
below:
鈥?PCV857-025 - 0 ps
鈥?PCV857-1300 - +50 ps
and when the PDB input is low. When the input
frequency increases to greater than approximately
20MHz, the PLL will be turned back on, the inputs and
outputs will be enabled, and the PLL will obtain phase
lock between the feedback clock pair (FB_INT,
FB_INC) and the input clock pair (CLK_INT, CLK_INC).
The PLL in the ASM5CVF857 clock driver uses the
input clocks (CLK_INT, CLKINC) and the feedback
clocks (FB_INT, FB_INC) to provide high-performance,
low-skew, low-jitter output differential clocks (CLKT[0:9],
CLKC[0:9]). ASM5CVF857 is also able to track spread
spectrum clock (SSC) for reduced EMI.
Product Description
This PLL clock buffer is designed for a V
DD
of 2.5V,
AV
DD
of 2.5V and differential data input a
nd output
ASM5CVF857 is characterized for operation from 0擄C
to 85擄C.
levels.
ASM5CVF857 is a zero-delay buffer that
Applications
鈥?/div>
鈥?/div>
DDR Memory Modules / Zero Delay Board Fan
Out.
Provides complete DDR DIMM logic solution with
ASM4SSTVF16857, ASM4SSTVF16859 &
ASM4SSTVF32852.
distributes a differential clock input pair (CLK_INT,
CLK_INC) to ten differential pairs of clock outputs
(CLKT[0:9], CLKC[0:9]) and one differential
pair
feedback clock output (FB_OUT, FB_OUTC). The clock
outputs are controlled by the input clocks (CLK_INT,
CLKINC), the feedback clocks (FB_INT, FB_INC), the
2,5V LVCMOS input (PDB), and the analog power input
(AV
DD
). When input (PDB) is low while power is applied,
the receivers are disabled, the PLL is turned off, and
the differential clock outputs are tri-stated. When AV
DD
is grounded, the PLL is turned off and bypassed for test
purposes.
Specifications
鈥?/div>
鈥?/div>
Meets PC3200 specification for DDR-I 400 support.
Covers all DDRI speed grades.
Switching Characteristics
When the input frequency is less than the operating
frequency of the PLL, approximately 20MHz, the device
will enter a low power mode. An input frequency
detection circuit on the differential inputs, independent
from the input buffers, will detect the low frequency
鈥?/div>
鈥?/div>
鈥?/div>
CYCLE-CYCLE jitter : <50ps.
OUT-OUTPUT skew: <40ps.
Period jitter: 鹵30ps.
2.5V Wide-Range Frequency Clock Driver (60 MHz
鈥?200 MHz)
Notice: The information in this document is subject to change without notice.
1 of 15
ASM5CVF857-48VR相關(guān)型號PDF文件下載
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Clock Driver
alliance
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