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ASM3X2105AFTR Datasheet

  • ASM3X2105AFTR

  • Low Frequency EMI Reduction

  • 10頁

  • ALSC

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October 2003
rev 1.0
ASM3X2105A
Features
FCC approved method of EMI attenuation.
Generates a 1X or 錕?frac12; X low EMI spread spectrum
clock of the input frequency.
Input frequency range: 6MHz to 10 MHz.
Internal loop filter minimizes external components
and board space.
Frequency deviation: Maximum 鹵 1%.
SSON# control pin for spread spectrum enable
and disable options.
Low cycle-to-cycle jitter.
5.0V 鹵 5% operating voltage range.
TTL or CMOS compatible outputs.
Ultra-low power CMOS design.
Available in 8-pin SOIC and TSSOP.
signals. The ASM3X2105A allows significant system cost
savings by reducing the number of circuit board layers
ferrite beads, shielding and other passive components
that are traditionally required to pass EMI regulations.
The ASM3X2105A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.
The ASM3X2105A modulates the output of a single PLL
in order to 鈥渟pread鈥?the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal鈥檚 bandwidth is called 鈥榮pread
spectrum clock generation鈥?
Product Description
The ASM3X2105A is a versatile spread spectrum
frequency modulator designed specifically for input clock
frequencies from 6MHz to 12MHz. The ASM3X2105A
can generate an EMI reduced clock from crystal, ceramic
resonator, or system clock. The ASM3X2105A offers
frequency deviation of 鹵 1%.
The ASM3X2105A reduces electromagnetic interference
(EMI) at the clock source, allowing system wide reduction
of EMI of
down stream clock and data dependent
Applications
The ASM3X2105A is targeted towards EMI management
for high speed digital applications such as PC peripheral
devices, consumer electronics and embedded controller
systems.
Block Diagram
SR0
SSON#
VDD
DIV2
Modulation
XIN
Crystal
Oscillator
XOUT
Feedback
Divider
Frequency
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
MODOUT
VSS
Alliance Semiconductor
2575, Augustine Drive
鈥?/div>
Santa Clara, CA
鈥?/div>
Tel: 408.855.4900
鈥?/div>
Fax: 408.855.4999
鈥?/div>
www.alsc.com
Notice: The information in this document is subject to change without notice.

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