音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

ASM3P2762AF-06OR Datasheet

  • ASM3P2762AF-06OR

  • Low Power Peak EMI Reducing Solution

  • 12頁

  • ALSC

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

September 2005
rev 1.6
Low Power Peak EMI Reducing Solution
Features
Generates an EMI optimized clock signal at the
output.
Integrated loop filter components.
Operates with a 3.3V /2.5V Supply.
Operating current less than 6mA.
Low power CMOS design.
Input frequency range: 6MHz to 12MHz for 2.5V
: 6MHz to 13MHz for 3.3V
Generates a 1X low EMI spread spectrum clock of
the input frequency.
Frequency deviation: -1.25% (Typ) @ 10MHz Input
Frequency
Available in 6-pin TSOT-23, 8-pin SOIC and 8-pin
TSSOP packages.
ASM3P2762A
The ASM3P2762A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all digital method.
The ASM3P2762A modulates the output of a single PLL
in order to 鈥渟pread鈥?the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal鈥檚 bandwidth is called 鈥榮pread
spectrum clock generation鈥?
Applications
The ASM3P2762A is targeted towards all portable
devices with very low power requirements like MP3
players and digital still cameras.
Product Description
The ASM3P2762A is a versatile spread spectrum
frequency modulator designed specifically for a wide
range of clock frequencies. The ASM3P2762A reduces
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of
all clock
dependent signals. The ASM3P2762A allows significant
system cost savings by reducing the number of circuit
board layers ferrite beads, shielding that are traditionally
required to pass EMI regulations.
Key Specifications
Description
Supply voltages
Cycle-to-Cycle Jitter
Output Duty Cycle
Modulation Rate Equation
Frequency Deviation
Specification
V
DD
= 3.3V /2.5V
200pS (Max)
45/55%
F
IN
/256
-1.25% (Typ) @ 10MHz
Block Diagram
V
DD
PD
XIN
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
Modulation
PLL
XOUT
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
V
SS
Alliance Semiconductor
2575 Augustine Drive
鈥?/div>
Santa Clara, CA
鈥?/div>
Tel: 408.855.4900
鈥?/div>
Fax: 408.855.4999
鈥?/div>
www.alsc.com
Notice: The information in this document is subject to change without notice.

ASM3P2762AF-06OR相關(guān)型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！