February 2005
rev 0.4
ASM3P2508SP
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Features
Dual PLL based Architecture
Operates with a 3.3V 鹵0.3V supply.
Generates an EMI optimized Spread Spectrum
PCI Clock output
Generates a high accuracy non Spread T1 clock of
鹵25ppm accuracy.
Generates a non spread system reference clock
Low power CMOS design.
Input frequency: 25 MHz.
Outputs:
Sys_ REF_CLK: 20 MHz
T1 Clock: 25 MHz (鹵25 ppm)
PCI_CLK: 33.33MHz Spread Spectrum
Frequency deviation: -0.5% (Typ).
Available in 8L SOIC Package.
The
ASM3P2508SP
uses
the
most
efficient
and
optimized modulation profile approved by the FCC.
ASM3P2508SP modulates the output of a PLL in order to
鈥渟pread鈥?the bandwidth of a synthesized clock, and more
importantly, decreases the peak amplitudes of its
harmonics. This results in a significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal鈥檚 bandwidth is called 鈥榮pread
spectrum clock generation鈥?(SSCG).
In
addition
to
the
SSCG
output,
ASM3P2508SP
generates two high accuracy clock signals -
T1 Clock @ 25.00MHz with +/- 25ppm stability, and a
20MHz Sys_ REF_CLK.
Applications
The ASM3P2508SP is targeted towards Consumer,
Industrial, Data and Telecommunications applications.
Product Description
The ASM3P2508SP is a versatile Dual PLL based Clock
Synthesizer and Frequency Generator optimised and
designed specifically for three clock frequencies. The
PCI_CLK
output
from
ASM3P2508SP
reduces
Key Specifications
Description
Supply voltages
Input Frequency
Cycle-to-Cycle Jitter
Output Duty Cycle
Output Rise and Fall Time
SSC Modulation Rate
SSC Frequency Deviation
Specification
V
DD
= 3.3V 鹵0.3V
25 MHz
175 pS ( Max)
45/55%
1.1 nS (Max)
30KHz (Typ)
-0.5% (Typ)
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of all clock
dependent signals. ASM3P2508SP allows significant
system cost savings by reducing the number of circuit
board
layers,
ferrite
beads
&
shielding
that
are
traditionally required to pass EMI regulations.
Block Diagram
PWRDNB
V
DD
T1_CLK
Input
Divider
PLL 1
Output
Divider
Sys_REF_CLK
XIN/CLKIN
Osc
XOUT
PLL 2
Output
Divider
PCI_CLK
Modulation
V
SS
Alliance Semiconductor
2575, Augustine Drive
鈥?/div>
Santa Clara, CA
鈥?/div>
Tel: 408.855.4900
鈥?/div>
Fax: 408.855.4999
鈥?/div>
www.alsc.com
Notice: The information in this document is subject to change without notice.
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