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AS9C25512M2018L-133FI Datasheet

  • AS9C25512M2018L-133FI

  • 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2...

  • 1101.45KB

  • 30頁

  • ALSC

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September 2004
Preliminary Information
廬
AS9C25512M2018L
AS9C25256M2018L
2.5V 512/256K X 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
Features
鈥?True Dual-Port memory cells that allow simulta-
neous access of the same memory location
鈥?Organisation: 524,288/262,144 脳 18
[1]
鈥?Fully Synchronous, independent operation on
both ports
鈥?Selectable Pipeline or Flow-Through output
mode
鈥?Fast clock speeds in Pipeline output mode: 250
MHz operation (9Gbps bandwidth)
鈥?Fast clock to data access: 2.8ns for Pipeline out-
put mode
鈥?Asynchronous output enable control
鈥?Fast OE access times: 2.8ns
鈥?Double Cycle Deselect (DCD) for Pipeline Out-
put Mode
鈥?19/18
[1]
-bit counter with Increment, Hold and
Repeat features on each port
Note:
1. AS9C25512M2018L/AS9C25256M2018L
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Dual Chip enables on both ports for easy
depth expansion
Interrupt and Collision Detection Features
2.5 V power supply for the core
LVTTL compatible, selectable 3.3V or
2.5V power supply for I/Os, addresses,
clock and control signals on each port
Snooze modes for each port for standby
operation
15mA typical standby current in power
down mode
Available in 256-pin Ball Grid Array
(BGA), 144-pin Thin Quad Flatpack
(TQFP) and 208-pin fine pitch Ball Grid
Array (fpBGA)
Supports JTAG features compliant with
IEEE 1149.1
Selection guide
Feature
Minimum cycle time
Maximum Pipeline clock frequency
Maximum Pipeline clock access time
Maximum flow-through clock frequency
Maximum flow-through clock access time
Maximum operating current
Maximum snooze mode current
-250
4
250
2.8
150
6.5
TBD
18
-200
5
200
3.4
133
7.5
350
18
-166
6
166
3.6
100
10
300
18
-133
7.5
133
4.2
83
12
260
18
Units
ns
MHz
ns
MHz
ns
mA
mA
9/24/04; v.1.2
Alliance Semiconductor
P. 1 of 30
Copyright 漏 Alliance Semiconductor. All rights reserved.

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