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AS5SS256K36ADQ-8.5/IT Datasheet

  • AS5SS256K36ADQ-8.5/IT

  • x36 Fast Synchronous SRAM

  • 512.62KB

  • 16頁

  • ETC

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Austin Semiconductor, Inc.
256K x 36 SSRAM
Synchronous Burst SRAM
FEATURES
l
l
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l
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AS5SS256K36 &
AS5SS256K36A
PIN ASSIGNMENT
(Top View)
SSRAM
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Organized 256K x 36
Fast Clock and OE\ access times
Single +3.3V +0.3V/-0.165V power supply (V
DD
)
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL WRITE
Three chip enables for simple depth expansion and address
pipelining
Clock-controlled and registered addresses, data I/Os and
control signals
Internally self-timed WRITE cycle
Burst control (interleaved or linear burst)
Automatic power-down for portable applications
100-lead TQFP package for high density, high speed
Low capacitive bus loading
100-pin TQFP (DQ)
(2-chip enable version, 鈥淎鈥?indicator)
SA
SA
ADV\
ADSP\
ADSC\
OE\
BWE\
GW\
CLK
Vss
V
DD
SA
BWa\
B W b\
BWc\
B W d\
CE2
CE\
SA
SA
81
82
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100
OPTIONS
Timing
8.5ns/10ns/100MHz
10ns/15ns/66MHz
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Packages
100-pin TQFP (2-chip enable)
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Pinout
2-chip Enables
3-chip Enables
l
Operating Temperature Ranges
Military (-55
o
C to +125
o
C)
Industrial (-40
o
C to +85
o
C)
l
MARKING
-8.5
-10
DQ No. 1001
A
no indicator
XT
IT
DQPc
DQc
DQc
V
DD
Q
Vss
DQc
DQc
DQc
DQc
Vss
V
DD
Q
DQc
DQc
Vss
V
DD
NC
Vss
DQd
DQd
V
DD
Q
Vss
DQd
DQd
DQd
DQd
Vss
V
DD
Q
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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80
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60
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51
DQPb
DQb
DQb
V
DD
Q
Vss
DQb
DQb
DQb
DQb
Vss
V
DD
Q
DQb
DQb
Vss
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
DQPa
100-pin TQFP (DQ)
(3-chip enable version, no indicator)
SA
SA
ADV\
ADSP\
ADSC\
OE\
BWE\
GW\
CLK
Vss
V
DD
CE2\
BWa\
BWb\
BWc\
BWd\
CE2
CE\
SA
SA
81
82
83
84
85
86
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90
91
92
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100
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SA
SA
SA
SA
SA
SA
SA
NF
NF
V
DD
Vss
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
GENERAL DESCRIPTION
The AS5SS256K36 employs high-speed, low-power CMOS
designs that are fabricated using an advanced CMOS process.
This 8Mb Synchronous Burst SRAM integrates a 256K x
36 SRAM core with advanced synchronous peripheral circuitry
and a 2-bit burst counter. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single-clock
input (CLK). The synchronous inputs include all addresses, all
data inputs, active LOW chip enable (CE\), two additional chip
enables for easy depth expansion (CE2\, CE2), burst control
inputs (ADSC\, ADSP\, ADV\), byte write enables (BWx\) and
global write (GW\). Note that CE2\ is not available on the A
version.
DQPc
DQc
DQc
V
DD
Q
Vss
DQc
DQc
DQc
DQc
Vss
V
DD
Q
DQc
DQc
Vss
V
DD
NC
Vss
DQd
DQd
V
DD
Q
Vss
DQd
DQd
DQd
DQd
Vss
V
DD
Q
DQd
DQd
DQPd
1
2
3
4
5
6
7
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10
11
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14
15
16
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80
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59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
V
DD
Q
Vss
DQb
DQb
DQb
DQb
Vss
V
DD
Q
DQb
DQb
Vss
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
Vss
DQa
DQa
DQa
DQa
Vss
V
DD
Q
DQa
DQa
DQPa
50
49
48
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46
45
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For more products and information
please visit our web site at
www.austinsemiconductor.com
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
Powered by ICminer.com Electronic-Library Service CopyRight 2003
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SA
SA
SA
SA
SA
SA
SA
SA
NF
V
DD
Vss
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
1

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