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AS4SD4M16DG-10/IT Datasheet

  • AS4SD4M16DG-10/IT

  • 4 Meg x 16 SDRAM Synchronous DRAM Memory

  • 50頁

  • ETC

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SDRAM
Austin Semiconductor, Inc.
4 Meg x 16 SDRAM
Synchronous DRAM Memory
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Extended Testing Over -55擄C to +125擄 C and
Industrial Temp -40擄C to 85擄 C
WRITE Recovery (
t
WR
/
t
DPL
)
t
WR
= 2 CLK
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8 or full page
Auto Precharge and Auto Refresh Modes
Self Refresh Mode (Industrial, -40擄C to 85擄 C only)
4,096-cycle refresh
LVTTL-compatible inputs and outputs
Single +3.3V 鹵0.3V power supply
Longer lead TSOP for improved reliability
(OCPL*)
Short Flow / Long Flow Test Screening Options
AS4SD4M16
PIN ASSIGNMENT
(Top View)
54-Pin TSOP
OPTIONS
鈥?/div>
鈥?/div>
MARKING
4M16
No. 901
Note: 鈥淺鈥?indicates an active low.
Configurations
4 Meg x 16 (1 Meg x 16 x 4 banks)
Plastic Package - OCPL*
54-pin TSOP (400 mil)
DG
Timing (Cycle Time)
8ns; t
AC
= 6.5ns @ CL = 3 ( t
RP
- 24ns)
10ns; t
AC
= 9ns @ CL = 2
Operating Temperature Ranges
-Military (-55擄C to +125擄 C)
-Industrial Temp (-40擄C to 85擄 C)
鈥?/div>
-8
-10
鈥?/div>
XT
IT
4 Meg x 16
Configuration
1 Meg x 16 x 4 banks
Refresh Count
4K
Row Addressing
4K (A0-A11)
Bank Addressing
4 (BA0, BA1)
Column Addressing
256 (A0-A7)
KEY TIMING PARAMETERS
SPEED
GRADE
-8
-10
-8
-10
CLOCK
ACCESS TIME
FREQUENCY
CL = 2** CL = 3**
125 MHz
鈥?/div>
6.5ns
100 MHz
鈥?/div>
7ns
83 MHz
9ns
鈥?/div>
66 MHz
9ns
鈥?/div>
SETUP
TIME
2ns
3ns
2ns
3ns
HOLD
TIME
1ns
1ns
1ns
1ns
*Off-center parting line
**CL = CAS (READ) latency
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS4SD4M16
Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1

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