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March 2001

廬

AS4LC4M4E0

AS4LC4M4E1

4Mx4 CMOS DRAM (EDO) Family

Features

鈥?Organization: 4,194,304 words 脳 4 bits

鈥?High speed

- 50/60 ns RAS access time

- 25/30 ns column address access time

- 12/15 ns CAS access time

鈥?Low power consumption

- Active: 500 mW max

- Standby: 3.6 mW max, CMOS I/O

鈥?Extended data out

鈥?Refresh

- 4096 refresh cycles, 64 ms refresh interval for AS4LC4M4E0

- 2048 refresh cycles, 32 ms refresh interval for AS4LC4M4E1

- RAS-only or CAS-before-RAS refresh or self-refresh

鈥?TTL-compatible, three-state I/O

鈥?JEDEC standard package

- 300 mil, 24/26-pin SOJ

鈥?3V power supply

鈥?Industrial and commercial temperature available

Pin designation

Pin arrangement

SOJ

V

CC

I/O0

I/O1

WE

RAS

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

GND

I/O3

I/O2

CAS

OE

V

CC

I/O0

I/O1

WE

RAS

1

2

3

4

5

6

7

8

9

10

11

12

TSOP

24

23

22

21

20

19

18

17

16

15

14

13

GND

I/O3

I/O2

CAS

OE

Pin(s)

A0 to A11

RAS

CAS

WE

I/O0 to I/O3

OE

V

CC

GND

Description

Address inputs

Row address strobe

Column address strobe

Write enable

Input/output

Output enable

Power

Ground

AS4LC4M4E0

*NC/A11

A10

A0

A1

A2

A9

A8

A7

A6

A5

A4

*NC/A11

A10

A0

A1

A2

AS4LC4M4E0

A9

A8

A7

A6

A5

A4

A3

V

CC

A3

V

CC

GND

GND

* NC on 2K refresh version; A11 on 4K refresh version

Selection guide

Symbol

Maximum RAS access time

Maximum column address access time

Maximum CAS access time

Maximum output enable (OE) access time

Minimum read or write cycle time

Minimum fast page mode cycle time

Maximum operating current

Maximum CMOS standby current

t

RAC

t

CAA

t

CAC

t

OEA

t

RC

t

PC

I

CC1

I

CC5

AS4LC4M4E0/E1-50 AS4LC4M4E0/E1-60 Unit

50

25

12

13

80

25

120

1.0

60

30

15

15

100

30

110

1.0

ns

ns

ns

ns

ns

ns

mA

mA

4/11/01; V.1.1

Alliance Semiconductor

P. 1 of 15

Copyright 漏 Alliance Semiconductor. All rights reserved.

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