鈥?/div>
3 Regulated Voltages are provided
General Description
The APW7047 provides the power controls and protec-
tions for three output voltages on AGP/PCI Graphic Card
applications. It integrates two PWM controllers , one
SOURCE-SINK linear controller, as well as the monitor
and protection functions into a single package. One PWM
converter (PWM1) regulates the VCORE(1.5V) for the GPU
with a SYNC. buck converter. The other standard buck
converter (PWM2) regulates the VMEM(2.5V) for the pow-
er of DDR memory. The SOURCE-SINK linear controller
control two external MOSFETs to be a linear regulator
with the capability of sourcing and sinking current. It reg-
ulates the VTT (1.25V) power for DDR Termination voltage.
Additional built-in over-voltage protection (OVP) will be
started when the VCORE or VMEM output is above 115%
of each DAC setting (V
CORE
and V
MEM
). OVP function will
shutdown the all output voltages until re-powering on the
IC. For each PWM converter, the over-current function
monitors the output current by sensing the voltage drop
across the MOSFET鈥榮 r
DS(ON)
, eliminating the need for a
current sensing resistor.
鈭?/div>
SYNC. Buck Converter for VCORE
(1.15V~1.50V)
鈭?/div>
Standard Buck Converter for VMEM
(2.40V~2.75V)
鈭?/div>
Linear Controller with SOURCE-SINK
Regulation for VTT(1.25V)
鈥?/div>
鈥?/div>
Simple Single-Loop Control Design
鈭?/div>
Voltage-Mode PWM Control
Excellent Output Voltage Regulation
鈭?/div>
VCORE Output : 鹵2% Over Temperature
鈭?/div>
VMEM Output : 鹵2% Over Temperature
鈭?/div>
VTT Output : 1/2 VIN 鹵25mV Over
Temperature Min. VIN = 1.7V
鈥?/div>
Fast Transient Response
鈭?/div>
Built-in Feedback Compensation
鈭?/div>
Full 0% to 100% Duty Ratio
鈥?/div>
鈥?/div>
鈥?/div>
Over-Voltage and Over-Current Fault Monitor
Constant Frequency Operation(200kHz)
24 pins, SOIC Package
Pin Description
VCC
1
UGATE
24
BOOT
2
23
UGATE 2
PHASE2
22
PHASE2
LGATE1
21
PG ND
20
MEM2
19
MEM1
18
MEM0
17
CORE2
16
CORE1
15
CORE0
14
OCSET2
13
VSE N2
UGATE 1
2
Applications
鈥?/div>
鈥?/div>
鈥?/div>
M/B DDR Power Regulation
AGP/PCI Graphics Power Regulation
SSTL-2 Termination
PHASE1
3
SS
SD
4
5
SO URCE
6
SINK
7
FB
VIN
8
9
OCSET1
10
VSE N1
11
GND
12
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright
錚?/div>
ANPEC Electronics Corp.
Rev.A.1 - May., 2002
1
www.anpec.com.tw
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