鈥?/div>
DDR I/II SDRAM Termination
SSTL-2/3 Termination Voltage
Applications Requiring the Regulator with
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VC N TL
VCN TL
VCN TL
VCN TL
VOUT
VREF
VCNTL
GND
VIN
VR EF
VO U T
TAB is VCNTL
SOP-8 (Top View)
VIN
TO-252-5 (Top View)
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3
2
1
VOUT
VREF
VCNTL
GND
VIN
Bi-direction 3A Current Capability
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NC
NC
General Description
The APL5331 linear regulator is designed to provide
a regulated voltage with bi-directional output current
for DDR-SDRAM termination. The APL5331 integrates
two power transistors to source or sink current up to
3A. It also incorporate current-limit, thermal shut-
down and shutdown control functions into a single
chip. Current-limit circuit limits the short-circuit
current.
GND
VREF
VOUT
TAB is VCNTL
VCNTL
NC
SOP-8-P (Top View)
NC = No internal connection
TO-263-5 (Top View)
= Thermal Pad
(connected to GND plane for better heat
dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright
錚?/div>
ANPEC Electronics Corp.
Rev. A.8 - Oct., 2003
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www.anpec.com.tw
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