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AD6122ARSRL Datasheet

  • AD6122ARSRL

  • CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Re...

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a
FEATURES
Fully Compliant with IS98A and PCS Specifications
Linear IF Amplifier
鈥?3 dB to +34 dB
Linear-in-dB Gain Control
Temperature-Compensated Gain Control
Quadrature Modulator
Modulates IFs from 50 MHz to 350 MHz
Integral Low Dropout Regulator
Accepts 2.9 V to 4.2 V Input from Battery
Low Power
10.4 mA at Midgain
<10 A Sleep Mode Operation
Companion Receiver IF Chip Available (AD6121)
APPLICATIONS
CDMA, W-CDMA, AMPS and TACS Operation
QPSK Transmitters
GENERAL DESCRIPTION
CDMA 3 V Transmitter IF Subsystem
with Integrated Voltage Regulator
AD6122
range IF amplifiers with voltage-controlled gain and a power-
down control input. An integral low dropout regulator allows
operation from battery voltages from 2.9 V to 4.2 V.
The gain control input accepts an external gain control voltage
input from a DAC. It provides 97 dB of gain control with a
nominal 75 dB/V scale factor. Either an internal or an external
reference may be used to set the gain-control scale factor.
The I and Q modulator accepts differential quadrature base-
band inputs from a CDMA baseband converter. The local oscil-
lator is injected at twice the IF frequency. A divide-by-two
quadrature generator followed by dual polyphase filters ensures
鹵
1擄 quadrature accuracy.
The modulator provides a common-mode reference output to
bias the transmit DACs in the baseband converter to the same
common-mode voltage as the modulator inputs, allowing dc
coupling between the two ICs and thus eliminating the need to
charge and discharge coupling capacitors. This allows the fastest
power-up and power-down times for the AD6122 and CDMA
baseband ICs.
The AD6122 is fabricated using a 25 GHz f
t
silicon BiCMOS
process and is packaged in a 28-lead SSOP and a 32-leadless
LPCC chip scale package (5 mm
脳
5 mm).
The AD6122 is a low power IF transmitter subsystem, specifi-
cally designed for CDMA applications. It consists of an I and Q
modulator, a divide-by-two quadrature generator, high dynamic
FUNCTIONAL BLOCK DIAGRAM
VCC
QUADRATURE
MODULATOR
OUTPUT
QUADRATURE MODULATOR
I INPUT
ATTENUATOR
IF AMPLIFIER
INPUT
IF AMPLIFIERS
LOCAL
OSCILLATOR
INPUT
Q INPUT
COMMON-MODE
REFERENCE
OUTPUT
VPOS
LOW
DROPOUT
REGULATOR
VREG
2
TRANSMIT
OUTPUT
AD6122
GAIN
CONTROL
SCALE
FACTOR
TEMPERATURE
COMPENSATION
POWER- POWER-
DOWN 1 DOWN 2
GAIN CONTROL
1.23 V
GAIN CONTROL
VOLTAGE
REFERENCE REFERENCE
INPUT
OUTPUT
VOLTAGE
INPUT
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
漏 Analog Devices, Inc., 2000

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