音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

AD6121ARSRL Datasheet

  • AD6121ARSRL

  • CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regul...

  • 16頁

  • AD

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

a
FEATURES
Fully Compliant with IS98A and PCS Specifications
CDMA, W-CDMA, AMPS, and TACS Operation
Linear IF Amplifier
5.9 dB Noise Figure
鈥?7.5 dB to +47 dB Linear-in-dB Gain Control
Quadrature Demodulator
Demodulates IFs from 50 MHz to 350 MHz
Integral Low Dropout Regulator
200 mV Voltage Drop
Accepts 2.9 V to 4.2 V Input from Battery
Low Power
10 mA at Midgain
<1 A Sleep Mode Operation
Companion Transmitter IF Chip Available (AD6122)
APPLICATIONS
CDMA, W-CDMA, AMPS, and TACS Operation
QPSK Receivers
CDMA 3 V Receiver IF Subsystem
with Integrated Voltage Regulator
AD6121
GENERAL DESCRIPTION
The AD6121 is a low power receiver IF subsystem specifically
designed for CDMA applications. It consists of high dynamic
range IF amplifiers with voltage controlled gain, a divide-by-two
quadrature generator, an I and Q demodulator, and a power-
down control input. An integral low dropout regulator allows
operation from battery voltages from 2.9 V to 4.2 V.
The gain control input accepts an external gain control voltage
input from a DAC. It provides 94.5 dB of gain control with a
nominal 52.5 dB/V scale factor when using an internal voltage
reference. The gain control interface reference input can be
connected to either the internal reference or an external reference.
The I and Q demodulator provides differential quadrature base-
band outputs to interface with CDMA baseband converters. A
divide-by-two quadrature generator followed by dual polyphase
filters ensures maximum
鹵
2.5擄 quadrature accuracy.
The AD6121 IF Subsystem is fabricated using a 25 GHz f
t
BiCMOS silicon process and is packaged in a 28-lead SSOP
and a 32-leadless LPCC chip scale package (5 mm
脳
5 mm).
FUNCTIONAL BLOCK DIAGRAM
ROOFING
FILTER
IF
OUTPUT
DEMODULATOR
INPUT
IOUT
CDMA
INPUT
IF AMPLIFIERS
IOUT
I
2
Q
LOCAL
OSCILLATOR
INPUT
QOUT
QOUT
QUADRATURE DEMODULATOR
FM
INPUT
INPUT STAGE
AD6121
VREG
PTAT
TEMPERATURE
COMPENSATION
GAIN CONTROL
SCALE FACTOR
LOW
DROPOUT
REGULATOR
VPOS
CDMA/FM
SELECT
GAIN
CONTROL
VOLTAGE
INPUT
POWER- POWER-
DOWN 2 DOWN 1
GAIN
1.23V
CONTROL REFERENCE
VOLTAGE
OUTPUT
REFERENCE
INPUT
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
漏 Analog Devices, Inc., 2000

AD6121ARSRL相關(guān)型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時(shí)間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！