a
FEATURES
Mixer
鈥?5 dBm 1 dB Compression Point
鈥? dBm IP3
24 dB Conversion Gain
>500 MHz Input Bandwidth
Logarithmic/Limiting Amplifier
80 dB RSSI Range
3 Phase Stability over 80 dB Range
Low Power
21 mW at 3 V Power Consumption
CMOS-Compatible Power-Down to 300
200 ns Enable/Disable Time
APPLICATIONS
PHS, GSM, TDMA, FM, or PM Receivers
Battery-Powered Instrumentation
Base Station RSSI Measurement
Low Power Mixer/Limiter/RSSI
3 V Receiver IF Subsystem
AD608
The RF and LO bandwidths both exceed 500 MHz. In a typical
IF application, the AD608 will accept the output of a 240 MHz
SAW filter and downconvert it to a nominal 10.7 MHz IF with
a conversion gain of 24 dB (Z
IF
= 165
鈩?.
The AD608鈥檚 loga-
rithmic/limiting amplifier section handles any IF from LF to as
high as 30 MHz.
The mixer is a doubly-balanced 鈥淕ilbert-Cell鈥?type and oper-
ates linearly for RF inputs spanning 鈥?5 dBm to 鈥?5 dBm. It
has a nominal 鈥? dBm third-order intercept. An onboard LO
preamplifier requires only 鈥?6 dBm of LO drive. The mixer鈥檚
current output drives a reverse-terminated, industry-standard
10.7 MHz 330
鈩?/div>
filter.
The nominal logarithmic scaling is such that the output is
+0.2 V for a sinusoidal input to the IF amplifier of 鈥?5 dBm
and +1.8 V at an input of +5 dBm; over this range the logarith-
mic conformance is typically
鹵
1 dB. The logarithmic slope is
proportional to the supply voltage. A feedback loop automati-
cally nulls the input offset of the first stage down to the sub-
microvolt level.
The AD608鈥檚 limiter output provides a hard-limited signal out-
put at 400 mV p-p. The voltage gain of the limiting amplifier to
this output is more than 100 dB. Transition times are 11 ns and
the phase is stable to within
鹵
3擄 at 10.7 MHz for signals from
鈥?5 dBm to +5 dBm.
The AD608 is enabled by a CMOS logic-level voltage input,
with a response time of 200 ns. When disabled, the standby
power is reduced to 300
碌W
within 400 ns.
The AD608 is specified for the industrial temperature range of
鈥?5擄C to +85擄C for 2.7 V to 5.5 V supplies and 鈥?0擄C to +85擄C
for 4.5 V to 5.5 V supplies. It comes in a 16-pin plastic SOIC.
W typ
GENERAL DESCRIPTION
The AD608 provides both a low power, low distortion, low
noise mixer and a complete, monolithic logarithmic/limiting
amplifier using a 鈥渟uccessive-detection鈥?technique. It provides
both a high speed RSSI (Received Signal Strength Indicator)
output with 80 dB dynamic range and a hard-limited output.
The RSSI output is from a two-pole post-demodulation low-
pass filter and provides a loadable output voltage of +0.2 V to
+1.8 V. The AD608 operates from a single 2.7 V to 5.5 V sup-
ply at a typical power level of 21 mW at 3 V.
FUNCTIONAL BLOCK DIAGRAM
24dB MIXER GAIN
3dB NOMINAL
INSERTION LOSS
IF INPUT
鈥?5dBm TO
+15dBm
2
7
BPF
DRIVER
VMID
MID-SUPPLY
IF BIAS
LOHI
BIAS
VPS1 COM1
1
+2.7V TO
5.5V
2
3
LO INPUT
鈥?6dBm
COM2
4
16
CMOS LOGIC
INPUT
NOTES:
1
2
110dB LIMITER GAIN
90dB RSSI
7 FULL-WAVE
RECTIFIER CELLS
IFHI
9
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
鹵6mA
MAX OUTPUT
(鹵890mV INTO 165鈩?
RFHI
RF INPUT
鈥?5 TO
鈥?5dBm
1
RFLO
6
LO
PREAMP
5
MIXER
鈮?/div>
2MHz
LPF
RSSI
RSSI OUTPUT
11 20mV/dB
0.2V TO 1.8V
鈮?/div>
MXOP
10.7MHz
BANDPASS
FILTER
330鈩?/div>
330鈩?/div>
10nF
COM3 12
VPS2
LMOP
FINAL
LIMITER
15 LIMITER
OUTPUT
400mVp-p
14 +2.7V TO 5.5V
8
100nF
100鈩?/div>
10
IFLO
13
18nF
FDBK
AD608
鹵50碌A
PRUP
鈥?5dBm =
鹵56mV
MAX FOR LINEAR OPERATION
39.76碌V RMS TO 397.6mV RMS FOR
鹵1dB
RSSI
ACCURACY
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
漏 Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD608AR 產(chǎn)品屬性
48
RF/IF 和 RFID
RF 混頻器
AD608
FM，GSM，PM，PHS，F(xiàn)M
500MHz
1
24dB
16dB
降頻變頻器
7.3mA
2.7 V ~ 5.5 V
管件
16-SOIC（0.154"，3.90mm 寬）
16-SOIC
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