40-Channel, 3 V/5 V, Single-Supply,
12-Bit, Voltage Output DAC
AD5381
FEATURES
Guaranteed monotonic
INL error: 鹵1 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/擄C reference
Temperature range: 鈥?0擄C to +85擄C
Rail-to-rail output amplifier
Power-down
Package type: 100-lead LQFP (14 mm 脳 14 mm)
User Interfaces:
Parallel
Serial (SPI廬/QSPI鈩?MICROWIRE鈩?DSP compatible,
featuring data readback)
2
I C廬 compatible
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via LDAC
Clear function to user programmable code
Amplifier boost mode to optimize slew rate
User programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitors
APPLICATIONS
Variable optical attenuators (VOA)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMs)
Control systems
Instrumentation
AGND (脳5)
DAC GND (脳5)
REFGND
REFOUT/REFIN
SIGNAL GND (脳5)
FUNCTIONAL BLOCK DIAGRAM
DVDD (脳3)
PD
SER/PAR
FIFO EN
CS/(SYNC/AD 0)
WR/(DCEN/AD 1)
SDO
DB11/(DIN/SDA)
DB10/(SCLK/SCL)
DB9/(SPI/I2C)
DB8
12
INPUT 12
REG 0
12
FIFO
+
STATE
MACHINE
+
CONTROL
LOGIC
12
m REG 0
c REG 0
R
12
INPUT 12
REG 1
12
12
m REG 1
c REG 1
R
VOUT4
12
POWER-ON
RESET
INPUT 12
REG 6
12
12
m REG 6
c REG 6
R
12
INPUT 12
REG 7
12
39-TO-1
MUX
12
m REG 7
c REG 7
R
03732-0-001
DGND (脳3)
AVDD (脳5)
AD5381
1.25V/2.5V
REFERENCE
12
DAC 12
REG 0
DAC 0
VOUT0
R
DB0
A5
A0
REG 0
REG 1
RESET
BUSY
CLR
INTERFACE
CONTROL
LOGIC
12
DAC 12
REG 1
DAC 1
VOUT1
VOUT2
R
VOUT3
12
DAC 12
REG 6
DAC 6
VOUT5
VOUT6
R
V
OUT
0鈥︹€︹€
OUT
38
12
DAC 12
REG 7
DAC 7
VOUT7
VOUT8
R
VOUT38
脳5
VOUT 39/MON_OUT
LDAC
Figure 1.
Rev. A
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