40-Channel, 14-Bit, Parallel and
Serial Input, Bipolar Voltage-Output DAC
AD5379
FEATURES
40-channel DAC in 13 mm 脳 13 mm 108-lead CSPBGA
Guaranteed monotonic to 14 bits
Buffered voltage outputs
Output voltage span of 3.5 V 脳 V
REF
(+)
Maximum output voltage span of 17.5 V
System calibration function allowing user-programmable
offset and gain
Pseudo differential outputs relative to REFGND
Clear function to user-defined REFGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
DAC increment/decrement mode
Channel grouping and addressing features
Interface options:
Parallel interface
DSP/microcontroller-compatible 3-wire serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
SDO daisy-chaining option
Power-on reset
Digital reset (RESET pin and soft reset function)
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
FUNCTIONAL BLOCK DIAGRAM
V
CC
POWER-ON
RESET
RESET
FIFOEN
DCEN/WR
SYNC/CS
14
V
DD
V
SS
AGND
DGND
LDAC
V
BIAS
V
REF
1(+) V
REF
1(鈥? REFGND A1
VBIAS
CLR
AD5379
/
FIFO
REG0
REG1
DB13
SCLK/DB12
DIN/DB11
INPUT
14
REG
0鈥?
14
/
m REG0鈥?
c REG0鈥?
14
/
DAC
14
REG
0鈥?
VOUT 0
/
DAC 0鈥?
VOUT 1
/
14
INTERFACE
DB0
A7
/
INPUT 14
REG
2
14
/
m REG2
c REG2
14
/
DAC 14
REG
2
/
DAC 2
VOUT 2
VOUT 3
VOUT 4
VOUT 5
A0
SER/PAR
DIN
SCLK
SDO
STATE MACHINE
14
/
14
/
/
INPUT
14
REG
7
14
/
m REG7
c REG7
14
/
DAC
14
REG
7
VOUT 6
/
DAC 7
VOUT 7
/
/
REFGND B1
REFGND B2
REFGND C1
REFGND C2
REFGND D1
REFGND D2
BUSY
14
14
/
INPUT 14
REG
8鈥?
14
/
DAC 14
REG
8鈥?
VOUT 8
/
DAC 8鈥?
VOUT 9
VOUT 10
03165-prT-001
/
m REG8鈥?
c REG8鈥?
脳4
V
REF
2(+) V
REF
2(鈥? REFGND A2
VOUT 39
Figure 1.
AD5379鈥擯rotected by U.S. Patent No. 5,969,657; other patents pending.
Rev. 0
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infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.
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