音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

AD5331 Datasheet

  • AD5331

  • 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Ou...

  • 352.01KB

  • 20頁

  • AD

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預覽

a
2.5 V to 5.5 V, 115 A, Parallel Interface
Single Voltage-Output 8-/10-/12-Bit DACs
AD5330/AD5331/AD5340/AD5341*
GENERAL DESCRIPTION
FEATURES
AD5330: Single 8-Bit DAC in 20-Lead TSSOP
AD5331: Single 10-Bit DAC in 20-Lead TSSOP
AD5340: Single 12-Bit DAC in 24-Lead TSSOP
AD5341: Single 12-Bit DAC in 20-Lead TSSOP
Low Power Operation: 115 A @ 3 V, 140 A @ 5 V
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via
PD
Pin
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0鈥揤
REF
or 0鈥? V
REF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via
LDAC
Pin
Asynchronous
CLR
Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Ampli鏗乪rs
Temperature Range: 鈥?0 C to +105 C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
The AD5330/AD5331/AD5340/AD5341 are single 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply con-
suming just 115
碌A
at 3 V, and feature a power-down mode that
further reduces the current to 80 nA. These devices incorporate
an on-chip output buffer that can drive the output to both
supply rails, while the AD5330, AD5340, and AD5341 allow a
choice of buffered or unbuffered reference input.
The AD5330/AD5331/AD5340/AD5341 have a parallel interface.
CS
selects the device and data is loaded into the input registers
on the rising edge of
WR.
The GAIN pin allows the output range to be set at 0 V to V
REF
or 0 V to 2
脳
V
REF
.
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the
LDAC
pin.
An asynchronous
CLR
input is also provided, which resets the
contents of the Input Register and the DAC Register to all zeros.
These devices also incorporate a power-on reset circuit that ensures
that the DAC output powers on to 0 V and remains there until
valid data is written to the device.
The AD5330/AD5331/AD5340/AD5341 are available in Thin
Shrink Small Outline Packages (TSSOP).
AD5330 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
V
REF
V
DD
POWER-ON
RESET
AD5330
BUF
GAIN
DB
7
.
.
DB
0
CS
WR
RESET
CLR
LDAC
POWER-DOWN
LOGIC
INTER-
FACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
8-BIT
DAC
BUFFER
V
OUT
PD
GND
*Protected
by U.S. Patent Number 5,969,657; other patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
漏 Analog Devices, Inc., 2000

AD5331相關型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務：
賣家服務：
技術客服：

0571-85317607

網(wǎng)站技術支持

13606545031

客服在線時間周一至周五
9:00-17:30

關注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！