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AD2S93BP Datasheet

  • AD2S93BP

  • Low Cost LVDT-to-Digital Converter

  • 349.27KB

  • 12頁(yè)

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a
FEATURES
Full Function Monolithic LVDT-to-Digital Converter
Absolute Serial Data Output
Uncommitted Differential Input
Repeatability
Remote Diagnostics
14-Bit Resolution
Industrial Temperature Range
28-Pin PLCC
Low Power
APPLICATIONS
Industrial Gauging
Industrial Process Control
Linear Positioning Systems
Linear Actuator Control
Automotive Motion Sensing and Control
Torque Sensing Conditioner
AC Strain Gages Conditioning
Avionics
REFERENCE
(PRIMARY
EXCITATION)
Low Cost
LVDT-to-Digital Converter
AD2S93
FUNCTIONAL BLOCK DIAGRAM
C3
ACERROR
ERROR
AMP
AC RATIO
BRIDGE
R6
C4 R5
DEMODIN
REF
DIFFERENTIAL
(SECONDARY A
VOLTAGE)
B
R4
GAIN
DIFF
R3
V
DD
LOS
OVR
UNR
NULL
CS
LATCHES
LOS
DECODE
LOGIC
UP-DOWN
COUNTER
PHASE
SENSITIVE
DEMODULATOR
DEMOD OUT
R1
R7
INTIN
C1
R2
C2
VEL
VCO GAIN
DIR
CLKOUT
FREQUENCY
SHAPING
VCO
DATA
SCLK
SERIAL
INTERFACE
AD2S93
GENERAL DESCRIPTION
The AD2S93 is a complete 14-bit resolution tracking LVDT-to-
digital converter. A Type II tracking loop is employed to track
the A鈥揃 input and produce a digital output equal to (A鈥揃)/
(REF/2), where REF is a fixed amplitude ac reference phase co-
herent with the A鈥揃 input. This allows the measurement of any
2-, 3-, 4- and 5-wire LVDT or linear amplitude modulated in-
put. The operating frequency range is from 360 Hz to 10 kHz
with user definable bandwidth set externally within a range of
45 Hz to 1250 Hz.
The AD2S93 has a 16-bit serial output. The MSB (LOS), read
first, indicates a loss of the signal A, B, or reference inputs to the
converter or transducer. The second and third MSBs are flags
indicating whether [鈥揜EF/2 (UNR)
鈮?/div>
A鈥揃
鈮?/div>
+REF/2 (OVR]) is
outside the linear operating range of the converter. The dis-
placement data is presented as 13-bit offset binary giving a
鹵
12-
bit operating range. LOS, OVR and UNR are pinned out on
the device, in addition a NULL flag is available which is set
when (A鈥揃) = 0.
Absolute displacement information is accessed when
CS
is taken
LO followed by the application of an external clock (SCLK)
with a maximum rate of 2 MHz. Data is read MSB first. When
CS
is high the DATA output is high impedance; this allows
daisy chaining of more than one converter onto a common bus.
The A, B differential input allows the user to scale the A, B in-
puts between 1 and 10. This enables the user to accurately set
up the inputs matching the REF input to the DIFF output. The
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
DIFF output is the resultant A鈥揃. The AD2S93 operates using
鹵
5 V
鹵
5% power supplies and is fabricated on Analog Devices鈥?/div>
linear compatible CMOS process (LC
2
MOS). The (LC
2
MOS)
is a mixed technology process that combines precision bipolar
circuits with low power logic.
PRODUCT HIGHLIGHTS
Complete LVDT-to-Digital Interface.
The AD2S93 pro-
vides the complete solution for digitizing LVDT signals to 14-
bit resolution.
Serial 16-Bit Output Data.
One 16-bit read from the
AD2S93 determines input signal continuity (LOS), over and
underrange detection and 13 bits of offset binary displacement
information.
High Accuracy Grade in Low Cost Package.
0.05% and
0.1% integral linearity over the full 鈥?0擄C to +85擄C operating
temperature range.
Uncommitted Differential Input.
Allows configuration of 2-,
3-, 4- and 5-wire LVDTs.
Multiple Converter Interfacing.
High impedance data out-
put and a simple three-wire interface reduces cabling and elimi-
nates bus contention.
Low Power.
70 mW power consumption (typ).
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

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