鈥?/div>
+
17 V
OUT
16
鈥揤
L
DL
DR 10
LR
11
18-BIT
D/A
18-BIT
LATCH
15
14 LL
13
DGND
CLK 12
The AD1864 is a complete dual 18-bit DAC offering excellent
THD+N, while requiring no external components. Two com-
plete signal channels are included. This results in cophased
voltage or current output signals and eliminates the need for
output demultiplexing circuitry. The monolithic AD1864 chip
includes CMOS logic elements, bipolar and MOS linear
elements and laser-trimmed thin-film resistor elements, all
fabricated on Analog Devices BiMOS II process.
The DACs on the AD1864 chip employ a partially-segmented
architecture. The first four MSBs of each DAC are segmented
into 15 elements. The 14 LSBs are produced using standard
R-2R techniques. Segment and R-2R resistors are laser-
trimmed to provide extremely low total harmonic distortion.
This architecture minimizes errors at major code transitions
resulting in low output glitch and eliminating the need for an
external deglitcher. When used in the current output mode, the
AD1864 provides two cophased
鹵
1 mA output signals.
Each channel is equipped with a high performance output
amplifier. These amplifiers achieve fast settling and high slew
rate, producing
鹵
3 V signals at load currents up to 8 mA. Each
output amplifier is short-circuit protected and can withstand
indefinite short circuits to ground.
The AD1864 was designed to balance two sets of opposing
requirements, channel separation and DAC matching. High
channel separation is the result of careful layout techniques. At
the same time, both channels of the AD1864 have been designed
to ensure matched gain and linearity as well as tracking over time
and temperature. This assures optimum performance when used in
stereo and multi-DAC per channel applications.
A versatile digital interface allows the AD1864 to be directly
connected to standard digital filter chips. This interface employs
five signals: Data Left (DL), Data Right (DR), Latch Left (LL),
Latch Right (LR) and Clock (CLK). DL and DR are the serial
input pins for the left and right DAC input registers. Input data
bits are clocked into the input register on the rising edge of
CLK. A low going latch edge updates the respective DAC
output. For systems using only a single latch signal, LL and LR
may be connected together. For systems using only one DATA
signal, DR and DL may be connected together.
The AD1864 operates from
鹵
5 V to
鹵
12 V power supplies. The
digital supplies, V
L
and 鈥揤
L
, can be separated from the analog
supplies, V
S
and 鈥揤
S
, for reduced digital feedthrough. Separate
analog and digital ground pins are also provided. The AD1864
typically dissipates only 225 mW, with a maximum power
dissipation of 265 mW.
The AD1864 is packaged in both a 24-pin plastic DIP and a
28-pin PLCC. Operation is guaranteed over the temperature
range of 鈥?5擄C to +70擄C and over the voltage supply range of
鹵
4.75 V to
鹵
13.2 V.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
The AD1864 is a complete dual 18-bit audio DAC.
108 dB signal-to-noise ratio for low noise operation.
THD+N is typically 0.0017%.
Interchannel gain and midscale matching.
Output voltages and currents are cophased.
Low glitch for improved sound quality.
Both channels are 100% tested at 8
脳
F
S
.
8. Low Power鈥攐nly 225 mW typ, 265 mW max.
9. Five-wire Interface for individual DAC control.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
漏 Analog Devices, Inc., 1997
1
2
3
4
5
6
7
8
9
10
11
12
