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a

PERFORMANCE FEATURES

ADSP-21060 Core Processor (.

. .

4)

480 MFLOPS Peak, 320 MFLOPS Sustained

25 ns Instruction Rate, Single-Cycle

Instruction Execution鈥揈ach of Four Processors

16 Mbit Shared SRAM (Internal to SHARCs)

4 Gigawords Addressable Off-Module Memory

Sixteen 40 Mbyte/s Link Ports (Four per SHARC)

Eight 40 Mbit/s Independent Serial Ports (Two

from Each SHARC)

5 V and 3.3 V Operation

32-Bit Single Precision and 40-Bit Extended

Precision IEEE Floating Point Data Formats, or

32-Bit Fixed Point Data Format

IEEE JTAG Standard 1149.1 Test Access Port and

On-Chip Emulation

PACKAGING FEATURES

452-Lead Ceramic Ball Grid Array (CBGA)

1.85" (47 mm) Body Size

0.200" Max Height

0.050" Ball Pitch

29 Grams (typical)

JC

= 0.36 C/W

LINK 1

LINK 2

TIMEXP

CS

Quad-SHARC

DSP Multiprocessor Family

AD14160/AD14160L

FUNCTIONAL BLOCK DIAGRAM

LINK 3

LINK 4

LINK 1

LINK 2

LINK 3

FLAG

3-0

TIMEXP

LINK 4

CS

FLAG

3-0

IRQ

2-0

IRQ

2-0

廬

TCK, TMS, TRST

EBOOT,

LBOOT,

BMS

EMU

CLKIN

EBOOT,

LBOOT, BMS

EMU

CLKIN

RESET

RESET

TCK, TMS, TRST

ID

2-0

CPA

SPORT 1

SPORT 0

TDI

LINK 0

LINK 5

TDO

LINK 0

LINK 5

TDI

SHARC_A

SHARC_B

ID

2-0

CPA

SPORT 1

SPORT 0

AD14160/

AD14160L

SHARC BUS (

ADDR

31-0

,

DATA

47-0

,

MS

3-0

,

RD, WR, PAGE, ADRCLK, SW, ACK,

SBTS, HBR, HBG, REDY, BR

6-1

, RPBA, DMAR

1.2

, DMAG

1.2

)

EBOOT,

LBOOT,

BMS

EMU

CLKIN

EBOOT,

LBOOT, BMS

EMU

CLKIN

RESET

TCK, TMS, TRST

RESET

TCK, TMS, TRST

FLAG

3-0

LINK 1

LINK 2

LINK 3

LINK 4

LINK 1

LINK 2

LINK 3

LINK 4

IRQ

2-0

GENERAL DESCRIPTION

The AD14160/AD14160L Quad-SHARC Ceramic Ball Grid

Array (CBGA) puts the power of the first generation AD14060

(CQFP) DSP multiprocessor into a very high density ball grid

array package; now with additional link and serial I/O pinned

out, beyond that from the CQFP package. The core of the multi-

processor is the ADSP-21060 DSP microcomputer. The AD14x60

modules have the highest performance鈥攄ensity and lowest

cost鈥?performance ratios of any in their class. They are ideal

for applications requiring higher levels of performance and/or

functionality per unit area.

The AD14160/AD14160L takes advantage of the built-in

multiprocessing features of the ADSP-21060 to achieve 480 peak

MFLOPS with a single chip type, in a single package. The on-

chip SRAM of the DSPs provides 16 Mbits of on-module

shared SRAM. The complete shared bus (48 data, 32 address)

is also brought off-module for interfacing with expansion

memory or other peripherals.

The ADSP-21060 link ports are interconnected to provide

direct communication among the four SHARCs as well as high

speed off-module access. Internally, links connect the SHARC

in a ring. Externally, each SHARC has a total of 160 Mbytes/s

link port bandwidth.

Multiprocessor performance is enhanced with embedded power

and ground planes, matched impedance interconnect, and opti-

mized signal routing lengths and separation. The fully tested

and ready-to-insert multiprocessor also significantly reduces

board space.

SHARC is a registered trademark of Analog Devices, Inc.

s

s

s

s

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

漏 Analog Devices, Inc., 1998

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

IRQ

2-0

CS

CS

LINK 5

TDI

LINK 5

TDO

FLAG

3-0

TIMEXP

TIMEXP

ID

2-0

CPA

SPORT 1

SPORT 0

TDO

SHARC_D

LINK 0

LINK 0

SHARC_C

ID

2-0

CPA

SPORT 1

SPORT 0

TDI

TDO

next

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