鈥?/div>
3
4
5
6
7
8
14
13
12
11
10
9
DESCRIPTION
The ABX0235 (PECL with inverted OE), ABX0237
(CMOS), ABX0238 (PECL), and ABX0239 (LVDS)
are high performance and low phase noise XO IC
chips. They provide phase noise performance as low
as 鈥?25dBc at 1kHz offset (at 155MHz) and a typical
RMS jitter of 4pS RMS ( at 155MHz ). They accept
fundamental parallel resonant mode crystals from 12
to 25MHz.
XIN
SEL0^ / VDD*
10
VDD / GND*
XOUT
SEL3^
SEL2^
OE
13
14
15
16
12
11
SEL1^
9
8
7
6
5
GND
CLKC
VDD
CLKT
ABX023x
1
2
3
4
GND
GND
GND
BLOCK DIAGRAM
SEL
OE
PLL
(Phase
Locked
Loop)
^:
*:
Internal pull-up
On 3x3 package, ABX0235/38 do not have SEL0 available: Pin 10
is VDD, pin 11 is GND. However, ABX0237/39 have SEL0 (pin
10), and pin 11 is VDD. See pin assignment table for details.
OUTPUT ENABLE LOGICAL LEVELS
Part #
ABX0238
ABX0235
ABX0237
ABX0239
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
Q
Q
XIN
XOUT
Oscillator
Amplifier
PLL by-pass
OE input: Logical states defined by PECL levels for ABX0238
Logical states defined by CMOS levels for
ABX0235/37/39
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001
www.Abracon.com
03/21/05 Page 1
GND