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A54SX16P-1PQ208 Datasheet

  • A54SX16P-1PQ208

  • 54SX Family FPGAs

  • 407.42KB

  • 57頁

  • ETC

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v3.1
54SX Family FPGAs
Le a di ng E dg e P er f or m a nc e
F ea t u r es
鈥?320 MHz Internal Performance
鈥?3.7 ns Clock-to-Out (Pin-to-Pin)
鈥?0.1 ns Input Set-Up
鈥?0.25 ns Clock Skew
Sp e ci f ic at ion s
鈥?66 MHz PCI
鈥?CPLD and FPGA Integration
鈥?Single Chip Solution
鈥?100% Resource Utilization with 100% Pin Locking
鈥?3.3V Operation with 5.0V Input Tolerance
鈥?Very Low Power Consumption
鈥?Deterministic, User-Controllable Timing
鈥?Unique In-System Diagnostic and Debug capability with
Silicon Explorer II
鈥?Boundary Scan Testing in Compliance with IEEE Standard
1149.1 (JTAG)
鈥?Secure Programming Technology Prevents Reverse
Engineering and Design Theft
鈥?12,000 to 48,000 System Gates
鈥?Up to 249 User-Programmable I/O Pins
鈥?Up to 1080 Flip-Flops
鈥?0.35碌 CMOS
S X P r od u c t P ro fi l e
A54SX08
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Clocks
JTAG
PCI
Clock-to-Out
Input Set-Up (External)
Speed Grades
Temperature Grades
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
8,000
12,000
768
512
256
130
3
Yes
鈥?/div>
3.7 ns
0.8 ns
Std, 鈥?, 鈥?, 鈥?
C, I, M
84
208
100
144, 176
鈥?/div>
144
A54SX16
16,000
24,000
1,452
924
528
175
3
Yes
鈥?/div>
3.9 ns
0.5 ns
Std, 鈥?, 鈥?, 鈥?
C, I, M
鈥?/div>
208
100
176
鈥?/div>
鈥?/div>
A54SX16P
16,000
24,000
1,452
924
528
175
3
Yes
Yes
4.4 ns
0.5 ns
Std, 鈥?, 鈥?, 鈥?
C, I, M
鈥?/div>
208
100
144, 176
鈥?/div>
鈥?/div>
A54SX32
32,000
48,000
2,880
1800
1,080
249
3
Yes
鈥?/div>
4.6 ns
0.1 ns
Std, 鈥?, 鈥?, 鈥?
C, I, M
鈥?/div>
208
鈥?/div>
144, 176
313, 329
鈥?/div>
June 2003
1
漏 2003 Actel Corporation

A54SX16P-1PQ208 產(chǎn)品屬性

  • 24

  • 集成電路 (IC)

  • 嵌入式 - FPGA（現(xiàn)場可編程門陣列）

  • SX

  • 1452

  • -

  • -

  • 175

  • 24000

  • 3 V ~ 3.6 V，4.75 V ~ 5.25 V

  • 表面貼裝

  • 0°C ~ 70°C

  • 208-BFQFP

  • 208-PQFP（28x28）

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