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A3980KLP Datasheet

  • A3980KLP

  • Automotive DMOS Microstepping Driver with Translator

  • 512.33KB

  • 18頁

  • ALLEGRO   ALLEGRO

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A3980
Automotive DMOS Microstepping Driver with Translator
Package LP
SENSE1
SR
DIR
OUT1A
PFD
RC1
AGND
REF
RC2
1
2
3
4
VBB1 28 VBB1
27 SLEEP
26 ENABLE
25 OUT1B
Data Sheet
26184.26A
The A3980 is a complete microstepping motor driver with built-in
translator for easy operation. It is designed to operate bipolar stepper
motors in full-, half-, eighth-, and sixteenth-step modes, at up to 35 V
and 鹵1 A. The A3980 includes a
鏗?/div>
xed off-time current regulator which
has the ability to operate in slow, fast, or mixed decay modes. This
results in reduced audible motor noise, increased step accuracy, and
reduced power dissipation.
The translator is the key to the easy implementation of the A3980.
Simply inputting one pulse on the step input drives the motor one
microstep. There are no phase sequence tables, high frequency control
lines, or complex interfaces to program. The A3980 interface is an ideal
鏗?/div>
t for applications where a complex 碌P is unavailable or overburdened.
Internal synchronous recti鏗乧ation control circuitry is provided to
improve power dissipation during PWM operation.
Internal circuit protection includes: thermal shutdown with hysteresis,
overvoltage lockout (OVLO), undervoltage lockout (UVLO), and
crossover current protection. Special power-up sequencing is not
required. In addition, two diagnostic fault
鏗?/div>
ags provide indication of
shorts or opens on the motor windings.
The A3980 is supplied in a low-pro鏗乴e (1.1 mm) 28L TSSOP with
exposed thermal pad (part number suf鏗亁
LP).
PWM
Timer
5
6
7
8
9
24 CP2
Translator
& Control Logic
Charge
Pump
Reg
23 CP1
22 VCP
21 PGND
20 VREG
19 STEP
18 OUT2B
17 FF2
16 FF1
梅
8
VDD 10 VDD
OUT2A 11
MS2 12
MS1 13
SENSE2 14
VBB2 15 VBB2
Approximate Scale 1:1
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, 500 ms,V
BB
.....................50
V
Logic Supply Voltage, V
DD
................................7.0
V
Logic Input Voltage
V
IN
.................................
鈥?.3 V to V
DD
+ 0.3 V
(t
W
< 30 ns) .......................
鈥?.0 V to V
DD
+ 1 V
Sense Voltage, V
SENSE
.......................................0.5
V
Reference Voltage, V
REF
鈥︹€︹€?............
0 V to V
DD
Package Power Dissipation (T
A
= +25潞C), P
D
"High-K" PCB
1
..............................R
胃JA
28潞C/W
Typical PCB
2
..................................R
胃JA
38潞C/W
Operating Temperature Range
Junction Temperature, T
J
...........鈥?0擄C
to +150擄C
Storage Temperature, T
S
..........鈥?5擄C
to +150擄C
1
Measured on a JEDEC-standard "High-K" 4-layer PCB.
2
Measured on a typical two-sided PCB with 3 in.
2
copper
FEATURES
Typical application up to 鹵1 A, 35 V output rating
Low R
DS(ON)
outputs, 0.67
鈩?/div>
source, 0.54
鈩?/div>
sink typical
Automatic current decay mode detection/selection
3.0 V to 5.5 V logic supply voltage range
Mixed, fast, and slow current decay modes
Synchronous recti鏗乧ation for low power dissipation
Internal OVLO, UVLO, and thermal shutdown circuitry
Crossover current protection
Short to supply/ground and short/open load diagnostics
APPLICATIONS
Automotive stepper motors
Engine management
Headlamp positioning
Use the following complete part number when ordering:
Part Number
A3980KLP
Package
28-pin, TSSOP
Description
Exposed thermal pad
ground area.

A3980KLP 產(chǎn)品屬性

  • 50

  • 集成電路 (IC)

  • PMIC - 電機(jī)和風(fēng)扇控制器，驅(qū)動器

  • -

  • 步進(jìn)電機(jī)驅(qū)動器

  • -

  • 1

  • ± 1A

  • 7 V ~ 50 V

  • 3 V ~ 5.5 V

  • -40°C ~ 125°C

  • 表面貼裝

  • 28-SOIC（0.173"，4.40mm 寬）裸露焊盤

  • 28-TSSOP 裸露焊盤

  • 管件

A3980KLP相關(guān)型號PDF文件下載

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