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89TSF552BL Datasheet

  • 89TSF552BL

  • Traffic Manager Co-processor

  • 376.76KB

  • 30頁

  • IDT

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Traffic Manager Co-processor
Data Sheet
89TTM553
Preliminary Information*
Description
The 89TTM553 is a flow-based traffic management co-processor
that can be used in conjunction with the 89TTM552.
It has two major functional parts: the queue manager (QM) and the
FLQ scheduler. The QM is responsible for all the non-bandwidth func-
tions, which include managing up to 1 Million queuing structures,
handling cell and packet arrivals and departures from these queues, and
maintaining a database of congestion management and statistics
parameters for each flow queue (FLQ). The FLQ scheduler is respon-
sible for managing the FLQ bandwidth functions.
The 89TTM553 FLQ scheduler supports traffic scheduling on up to
1M discrete flows. In addition to the scheduling levels provided by the
89TTM552, the 89TTM553 provides one or two levels of additional
scheduling hierarchy. It also provides guaranteed minimum rate,
maximum rate capping, excess rate distribution using weighted fair
queuing (WFQ), byte rate shaping, and dynamic configuration adjust-
ments.
The 89TTM553 stores all the flow-based parameters (and state infor-
mation) that are made available to the 89TTM552 for flow-based
processing. When the 89TTM553 is used with the 89TTM552, conges-
tion and bandwidth management features are enabled at the flow level
as well as at the aggregate-flow level.
89TTM55x Features
Features
Deterministic performance at 10 Gbps wire-speed (35 Mcps)
regardless of the number of flows, traffic size, and patterns.
x
Up to 256 megabytes of external memory buffer space
(equivalent to a 210 ms buffer at 10 Gbps).
x
Support (Rx and Tx) for industry-standard SPI-4 phase 2,
NPF Streaming Interface, and CSIX over LVDS.
x
Hierarchical queuing and precise scheduling:
鈥?Traffic management flexibility.
鈥?Support for up to 4K aggregate flow queues (AFQs), 1K port
queues (PQs), 2K arrival reassembly queues (ARQs), and 1K
output queues/channels (OQs) with no external memory
required. Configurable AFQ-to-port assignments.
鈥?Support for up to 1M discrete flows (FLQs), with queuing for
each flow, using external memory. Configurable mapping of
FLQs into aggregate flow queues.
鈥?Two-level FLQ scheduling mode that supports up to 128K or
256K virtual pipe or subscriber queues with up to 8 or 4 CoS
priority queues each.
鈥?Accurate byte-rate shaping at the FLQ, AFQ and port levels.
x
Multiple levels of buffer congestion management.
鈥?Hierarchical queue structure and thresholding.
鈥?Congestion indication.
鈥?Dynamic adjustment of thresholds during periods of congestion.
鈥?Packet discard (PD).
鈥?Weighted random early discard (WRED).
鈥?Local congestion indication (CI).
x
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 of 30
錚?/div>
2005 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
March 3, 2005
DSC 6797

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