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80960CF-40 Datasheet

  • 80960CF-40

  • 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALA...

  • 77頁

  • INTEL   INTEL

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A
PRELIMINARY
80960CF-40, -33, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
EMBEDDED MICROPROCESSOR
鈥?Socket and Object Code Compatible with 80960CA
鈥?Two Instructions/Clock Sustained Execution
鈥?Four 71 Mbytes/s DMA Channels with Data Chaining
鈥?Demultiplexed 32-Bit Burst Bus with Pipelining
32-Bit Parallel Architecture
s
Four On-Chip DMA Channels
鈥?Two Instructions/clock Execution
鈥?71 Mbytes/s Fly-by Transfers
鈥?Load/Store Architecture
鈥?40 Mbytes/s Two-Cycle Transfers
鈥?Sixteen 32-Bit Global Registers
鈥?Data Chaining
鈥?Sixteen 32-Bit Local Registers
鈥?Data Packing/Unpacking
鈥?Manipulates 64-Bit Bit Fields
鈥?Programmable Priority Method
鈥?11 Addressing Modes
s
32-Bit Demultiplexed Burst Bus
鈥?Full Parallel Fault Model
鈥?128-Bit Internal Data Paths to
and
from
鈥?Supervisor Protection Model
Registers
Fast Procedure Call/Return Model
鈥?Burst Bus for DRAM Interfacing
鈥?Address Pipelining Option
鈥?Full Procedure Call in 4 Clocks
鈥?Fully Programmable Wait States
On-Chip Register Cache
鈥?Supports 8-, 16- or 32-Bit Bus Widths
鈥?Caches Registers on Call/Ret
鈥?Supports Unaligned Accesses
鈥?Minimum of 6 Frames Provided
鈥?Supervisor Protection Pin
鈥?Up to 15 Programmable Frames
s
High-Speed Interrupt Controller
On-Chip Instruction Cache
鈥?Up to 248 External Interrupts
鈥?4 Kbyte Two-Way Set Associative
鈥?32 Fully Programmable Priorities
鈥?128-Bit Path to Instruction Sequencer
鈥?Multi-mode 8-Bit Interrupt Port
鈥?Cache-Lock Modes
鈥?Four Internal DMA Interrupts
鈥?Cache-Off Mode
鈥?Separate, Non-maskable Interrupt Pin
High Bandwidth On-Chip Data RAM
鈥?Context Switch in 625 ns Typical
鈥?1 Kbyte On-Chip Data RAM
s
On-Chip Data Cache
鈥?Sustains 128 bits per Clock Access
鈥?1 Kbyte Direct-Mapped, Write Through
Selectable Big or Little Endian Byte
鈥?128 bits per Clock Access on Cache Hit
Ordering
s
s
s
s
s
s
漏 INTEL CORPORATION, 1996
June 1996
Order Number:
272886-001

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