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79RC32V334-150BBI Datasheet

  • 79RC32V334-150BBI

  • MICROPROCESSOR|32-BIT|BGA|256PIN|PLASTIC

  • 30頁

  • ETC

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RISCore
TM
32300 Family
Integrated Processor
79RC32334
Features
RC32300 32-bit Microprocessor
鈥?Up to 150 MHz operation
鈥?Enhanced MIPS-II Instruction Set Architecture (ISA)
鈥?Cache prefetch instruction
鈥?Conditional move instruction
鈥?DSP instructions
鈥?Supports big or little endian operation
鈥?MMU with 32 page TLB
鈥?8kB Instruction Cache, 2-way set associative
鈥?2kB Data Cache, 2-way set associative
鈥?Cache locking per line
鈥?Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
鈥?Compatible with a wide variety of operating systems
鈼?/div>
Local Bus Interface
鈥?Up to 75 MHz operation
鈥?26-bit address bus
鈥?32-bit data bus
鈥?Direct control of local memory and peripherals
鈥?Programmable system watch-dog timers
鈥?Big or little endian support
鈼?/div>
Interrupt Controller simplifies exception management
鈼?/div>
Four general purpose 32-bit timer/counters
鈼?/div>
Programmable I/O (PIO)
鈥?Input/Output/Interrupt source
鈥?Individually programmable
鈼?/div>
SDRAM Controller (32-bit memory only)
鈥?4 banks, non-interleaved
鈥?Up to 256MB total SDRAM memory supported
鈥?Implements full, direct control of discrete, SODIMM, or DIMM
memories
鈥?Supports 16Mb through 256Mb SDRAM device depths
鈥?Automatic refresh generation
鈼?/div>
Serial Peripheral Interface (SPI) master mode interface
鈼?/div>
UART Interface
鈥?Two 16550 compatible UARTs
鈥?Baud rate support up to 1.5M
鈥?Modem control signals available on one channel
鈼?/div>
Memory & Peripheral Controller
鈥?6 banks, up to 64MB per bank
鈥?Supports 8-,16-, and 32-bit interfaces
鈥?Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
鈥?Supports external wait-state generation
鈥?8-bit boot PROM support
鈥?Flexible I/O timing protocols
鈼?/div>
Block Diagram
EJTAG
In-Circuit Emulator Interface
RISCore32300
RC5000
Enhanced MIPS-II ISA Compatible
Integer CPU
CP0
32-page
TLB
Interrupt Control
Programmable I/O
32-bit Timers
SPI Control
DMA Control
Local
Memory/IO
Control
Dual UART
IPBus
Bridge
2kB
2-set, Lockable
Data Cache
8kB
2-set
Lockable
Instr. Cache
Figure 1 RC32334 Block Diagram
IDT
Peripheral
Bus
PCI Bridge
SDRAM
Control
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 30
錚?/div>
2001 Integrated Device Technology, Inc.
May 2, 2002
DSC 5701

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