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79RC32V333-100DHI Datasheet

  • 79RC32V333-100DHI

  • Microprocessor

  • 28頁(yè)

  • ETC

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IDT
TM
Interprise
TM
Integrated
Communications Processor
79RC32333
Features
RC32300 32-bit Microprocessor
鈥?Up to 150 MHz operation
鈥?Enhanced MIPS-II Instruction Set Architecture (ISA)
鈥?Cache prefetch instruction
鈥?Conditional move instruction
鈥?DSP instructions
鈥?Supports big or little endian operation
鈥?MMU with 32 page TLB
鈥?8KB Instruction Cache, 2-way set associative
鈥?2KB Data Cache, 2-way set associative
鈥?Cache locking per line
鈥?Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
鈥?Compatible with a wide variety of operating systems
鈼?/div>
Local Bus Interface
鈥?Up to 75 MHz operation
鈥?23-bit address bus
鈥?32-bit data bus
鈥?Direct control of local memory and peripherals
鈥?Programmable system watch-dog timers
鈥?Big or little endian support
鈼?/div>
Interrupt Controller simplifies exception management
鈼?/div>
Four general purpose 32-bit timer/counters
鈼?/div>
Programmable I/O (PIO)
鈥?Input/Output/Interrupt source
鈥?Individually programmable
鈼?/div>
SDRAM Controller (32-bit memory only)
鈥?4 banks, non-interleaved
鈥?Up to 512MB total SDRAM memory supported
鈥?Implements full, direct control of discrete, SODIMM, or DIMM
memories
鈥?Supports 16Mb through 512Mb SDRAM device depths
鈥?Automatic refresh generation
鈼?/div>
Serial Peripheral Interface (SPI) master mode interface
鈼?/div>
UART Interface
鈥?16550 compatible UART
鈥?Baud rate support up to 1.5M
鈼?/div>
Memory & Peripheral Controller
鈥?6 banks, up to 8MB per bank
鈥?Supports 8-,16-, and 32-bit interfaces
鈥?Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
鈥?Supports external wait-state generation
鈥?8-bit boot PROM support
鈥?Flexible I/O timing protocols
鈼?/div>
Block Diagram
EJTAG
In-Circuit Emulator Interface
RISCore 32300
Enhanced MIPS-II ISA
Integer CPU
RC5000
Compatible
CP0
32-page
TLB
Interrupt Control
Programmable I/O
32-bit Timers
SPI Control
DMA Control
Local
Memory/IO
Control
UART
IPBus
Bridge
2KB
2-set, Lockable
Data Cache
8KB
2-set
Lockable
Instr. Cache
Figure 1 RC32333 Block Diagram
IDT
Peripheral
Bus
SDRAM
Control
PCI Bridge
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 28
錚?/div>
2002 Integrated Device Technology, Inc.
September 18, 2002
DSC 6209

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