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78P7200-IH/F Datasheet

  • 78P7200-IH/F

  • Line Interface Unit

  • 11頁

  • ETC

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78P7200
E3/DS3/STS-1
Line Interface Unit
DATA SHEET
JULY 2005
DESCRIPTION
The 78P7200 is a line interface transceiver IC
intended for STS-1 (51.84 Mbit/s), DS3 (44.736
Mbit/s) and E3 (34.368 Mbit/s) applications. The
receiver has a very wide dynamic range and is
designed to accept either HDB3 or B3ZS-encoded
Alternate-Mark Inversion (AMI) inputs; it provides
CMOS logic level clock, positive data, negative data
and low-level signal detector outputs. An on-chip
equalizer improves the intersymbol interference
tolerance on the receive path. The transmitter
converts CMOS logic level clock, positive data and
negative data input signals into AMI pulses of the
appropriate shape for transmission. A line buildout
(LBO) equalizer may be selected to shape the
outgoing pulses for shorter line lengths. The
78P7200 requires a single 5 volt supply and is
available in a surface mount package.
FEATURES
鈥?/div>
Single chip transmit and receive interface for
STS-1 (51.84 Mbit/s), E3 (34.368 Mbit/s) or DS3
(44.736 Mbit/s) applications
On-chip Receive Equalizer
Unique clock recovery circuit, requires no
crystals, tuned components or external clock
Selectable transmit line buildout (LBO) to
accommodate shorter line lengths
Compliant with ANSI T1.102-1993, Bellcore TR-
NWT-000499 and GR-253-CORE, ITU-T G.703
and G.823_1991
Low-level input signal indication
Available in a 28 PLCC surface mount package
-40擄C to +85擄C operating range
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
BLOCK DIAGRAM
LOWSIG
RVcc
CPD
RVcc
RLF2
RLF1
CLF1
RVcc
RFO
Low-Level Signal
Detection
Clock Recovery
RCLK
DVcc
LIN+
INPUT
LIN-
Eq.
Signal
Acquisition
Data
Detection
RPOS
RNEG
DGND
TVcc
LOUT+
OUTPUT
LOUT-
Output
Driver,
Line
Buildout
Pulse
Shaper
Pulse
Generator
TCLK
TPOS
TNEG
OPT@
LBO
OPT!
Page: 1 of 11
漏
2005 Teridian Semiconductor Corporation
Rev 3.0

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