74VHC573 Octal D-Type Latch with 3-STATE Outputs
March 1993
Revised May 2005
74VHC573
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHC573 is an advanced high speed CMOS octal latch
with 3-STATE output fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. This 8-bit D-type latch is con-
trolled by a latch enable input (LE) and an Output Enable
input (OE). When the OE input is HIGH, the eight outputs
are in a high impedance state.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: t
PD
5.0 ns (typ) at V
CC
V
NIL
5V
s
High Noise Immunity: V
NIH
s
Low Noise: V
OLP
28% V
CC
(Min)
s
Power Down Protection is provided on all inputs
0.6V (typ)
4
P
A (Max) @ T
A
25
q
C
s
Low Power Dissipation: I
CC
s
Pin and function compatible with 74HC573
Ordering Code:
Order Number
74VHC573M
74VHC573SJ
74VHC573MTC
74VHC573N
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
D
0
鈥揇
7
LE
OE
O
0
鈥揙
7
漏 2005 Fairchild Semiconductor Corporation
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Outputs
DS011563
www.fairchildsemi.com
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