74VHC541 Octal Buffer/Line Driver with 3-STATE Outputs
August 1993
Revised May 2005
74VHC541
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The VHC541 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The VHC541 is an octal buffer/line driver designed to be
employed as memory and address drivers, clock drivers
and bus oriented transmitter/receivers.
This device is similar in function to the VHC244 while pro-
viding flow-through architecture (inputs on opposite side
from outputs). This pinout arrangement makes this device
especially useful as an output port for microprocessors,
allowing ease of layout and greater PC board density.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: t
PD
3.5 ns (typ) at V
CC
V
NIL
5V
25
q
C
s
Low power dissipation: I
CC
s
High noise immunity: V
NIH
s
Low noise: V
OLP
4
P
A (max) at T
A
28% V
CC
(min)
s
Power down protection is provided on all inputs
0.9V (typ)
s
Pin and function compatible with 74HC541
Ordering Code:
Order Number
74VHC541M
74VHC541SJ
74VHC541MTC
74VHC541N
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
- I
7
O
0
- O
7
Descriptions
3-STATE Output Enable Inputs
Inputs
3-STATE Outputs
Truth Table
Inputs
OE
1
L
H
X
L
H HIGH Voltage Level
L LOW Voltage Level
Outputs
I
H
X
X
L
H
Z
Z
L
OE
2
L
X
H
L
X Immaterial
Z High Impedance
漏 2005 Fairchild Semiconductor Corporation
DS011639
www.fairchildsemi.com
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