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t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
IMPROVED LATCH-UP IMMUNITY
LOW NOISE V
OLP
= 0.9V (Max.)
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC273M
74VHC273T
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs .
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The 74VHC273 is an advanced high-speed
CMOS OCTAL
D-TYPE FLIP FLOP WITH
CLEAR fabricated with sub-micron silicon gate
and
double-layer metal
wiring
C
2
MOS
technology.
PIN CONNECTION AND IEC LOGIC SYMBOLS
October 1999
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