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74VHC139M Datasheet

  • 74VHC139M

  • DUAL 2 TO 4 DECODER/DEMULTIPLEXER

  • 8頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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廬
74VHC139
DUAL 2 TO 4 DECODER/DEMULTIPLEXER
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
=5.0 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 139
IMPROVED LATCH-UP IMMUNITY
M1
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC139M
74VHC139T
gating or as a data input for demultiplexing
applications. While the enable input is held high,
all four outputs are high independently of the
other inputs.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The 74VHC139 is an advanced high-speed
CMOS DUAL 2 TO 4 LINE DECODER/
DEMULTIPLEXER fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.
The active low enable input can be used for
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
1/8

74VHC139M 產(chǎn)品屬性

  • 48

  • 集成電路 (IC)

  • 邏輯 - 信號(hào)開關(guān)，多路復(fù)用器，解碼器

  • 74VHC

  • 解碼器/多路分解器

  • 1 x 2:4

  • 2

  • 8mA，8mA

  • 單電源

  • 2 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 16-SOIC（0.154"，3.90mm 寬）

  • 16-SOIC

  • 管件

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