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74VHC138M Datasheet

  • 74VHC138M

  • 3-to-8 Decoder/Demultiplexer

  • 7頁

  • FAIRCHILD

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74VHC138 3-to-8 Decoder/Demultiplexer
November 1992
Revised April 1999
74VHC138
3-to-8 Decoder/Demultiplexer
General Description
The VHC138 is an advanced high speed CMOS 3-to-8
decoder/demultiplexer fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
When the device is enabled, 3 binary select inputs (A
0
, A
1
and A
2
) determine which one of the outputs (O
0
鈥揙
7
) will go
LOW. When enable input E
3
is held LOW or either E
1
or E
2
is held HIGH, decoding function is inhibited and all outputs
go HIGH. E
3
, E
1
and E
2
inputs are provided to ease cas-
cade connection and for use as an address decoder for
memory systems. An input protection circuit ensures that
0V to 7V can be applied to the input pins without regard to
the supply voltage. This device can be used to interface 5V
to 3V systems and two supply systems such as battery
back up. This circuit prevents device destruction due to
mismatched supply and input voltages.
Features
s
High Speed: t
PD
=
5.7ns (typ) at T
A
=
25擄C
s
Low power dissipation: I
CC
=
4
碌A(chǔ)
(max.) at T
A
=
25擄C
s
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min.)
s
Power down protection provided on all inputs
s
Pin and function compatible with 74HC138
Ordering Code:
Order Number
74VHC138M
74VHC138SJ
74VHC138MTC
74VHC138N
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150鈥?Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
A
0
鈥揂
2
E
1
鈥揈
2
E
3
O
0
鈥揙
7
Description
Address Inputs
Enable Inputs
Enable Input
Outputs
漏 1999 Fairchild Semiconductor Corporation
DS011537.prf
www.fairchildsemi.com

74VHC138M 產(chǎn)品屬性

  • 48

  • 集成電路 (IC)

  • 邏輯 - 信號開關(guān)，多路復(fù)用器，解碼器

  • 74VHC

  • 解碼器/多路分解器

  • 1 x 3:8

  • 1

  • 8mA，8mA

  • 單電源

  • 2 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 16-SOIC（0.154"，3.90mm 寬）

  • 16-SOIC

  • 管件

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