74VHC125 Quad Buffer with 3-STATE Outputs
August 1993
Revised March 1999
74VHC125
Quad Buffer with 3-STATE Outputs
General Description
The VHC125 contains four independent non-inverting buff-
ers with 3-STATE outputs. It is an advanced high-speed
CMOS device fabricated with silicon gate CMOS technol-
ogy and achieves the high-speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: t
PD
=
3.8 ns (typ) at V
CC
=
5V
s
Lower power dissipation: I
CC
=
4
碌A(chǔ)
(max) at T
A
=
25擄C
s
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
s
Power down protection is provided on all inputs
s
Low noise: V
OLP
=
0.8V (max)
Ordering Code:
Order Number
74VHC125M
74VHC125SJ
74VHC125MTC
74VHC125N
Package Number
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
A
n
, B
n
O
n
Description
Inputs
Outputs
Function Table
Inputs
A
n
L
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
HIGH Impedance
X
=
Immaterial
Output
B
n
L
H
X
O
n
L
H
Z
漏 1999 Fairchild Semiconductor Corporation
DS011632.prf
www.fairchildsemi.com