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74VCX32500G Datasheet

  • 74VCX32500G

  • Low Voltage 36-Bit Universal Bus Transceivers with 3.6V Tole...

  • 150.73KB

  • 9頁

  • FAIRCHILD

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74VCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
March 2001
Revised August 2003
74VCX32500
Low Voltage 36-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX32500 is an 36-bit universal bus transceiver which
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB. When OEAB is HIGH, the outputs are
active. When OEAB is LOW, the outputs are in a high-
impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
The VCX32500 is designed for low voltage (1.4V to 3.6V)
V
CC
applications with I/O capability up to 3.6V.
The 74VCX32500 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Note 1:
To ensure the high-impedance state during power up or power
down, OEBA should be tied to V
CC
through a pull-up resistor and OEAB
should be tied to GND through a pull-down resistors; the minimum value of
the resistor is determined by the current-sourcing capability of the driver.
Features
s
1.4V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
(A to B, B to A)
2.9 ns max for 3.0V to 3.6V V
CC
s
Power-down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
Static Drive (I
OH
/I
OL
)
鹵
24 mA @ 3.0V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latchup performance exceeds 300 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
s
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number
74VCX32500G
(Note 2)(Note 3)
Package Number
BGA114A
Package Description
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 2:
Ordering Code 鈥淕鈥?indicates Trays.
Note 3:
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
漏 2003 Fairchild Semiconductor Corporation
DS500403
www.fairchildsemi.com

74VCX32500G 產(chǎn)品屬性

  • 720

  • 集成電路 (IC)

  • 邏輯 - 通用總線函數(shù)

  • 74VCX

  • 通用總線收發(fā)器

  • -

  • 36 位

  • 24mA，24mA

  • 1.4 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 114-LFBGA

  • 114-BGA

  • 管件

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