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74VCX162373MTD Datasheet

  • 74VCX162373MTD

  • Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inpu...

  • 7頁

  • FAIRCHILD

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74VCX162373 Low Voltage 16-Bit Transparent Latch
January 2000
Revised January 2000
74VCX162373
Low Voltage 16-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
and 26鈩?Series Resistors in Outputs
General Description
The VCX162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
The VCX162373 is also designed with 26鈩?resistors in the
outputs. This design reduces line noise in applications
such as memory address drivers, clock drivers and bus
transceivers/transmitters.
The 74VCX162373 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74VCX162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.65V鈥?.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
26鈩?series resistors in outputs
s
t
PD
(I
n
to O
n
)
3.3 ns max for 3.0V to 3.6V V
CC
4.5 ns max for 2.3V to 2.7V V
CC
9.0 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Support live insertion and withdrawal (Note 1)
s
Static Drive (I
OH
/I
OL
)
鹵12
mA @ 3.0V V
CC
鹵8
mA @ 2.3V V
CC
鹵3
mA @ 1.65V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 300 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Ordering Number
74VCX162373MTD
Package
Number
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
LE
n
I
0
鈥揑
15
O
0
鈥揙
15
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
漏 2000 Fairchild Semiconductor Corporation
DS500236
www.fairchildsemi.com

74VCX162373MTD 產品屬性

  • 38

  • 集成電路 (IC)

  • 邏輯 - 鎖銷

  • 74VCX

  • D 型透明鎖存器

  • 8:8

  • 三態(tài)

  • 1.4 V ~ 3.6 V

  • 2

  • 1ns

  • 12mA,12mA

  • -40°C ~ 85°C

  • 表面貼裝

  • 48-TFSOP(0.240",6.10mm 寬)

  • 48-TSSOP

  • 管件

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