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74V2G74CTR Datasheet

  • 74V2G74CTR

  • FLIP-FLOP|SINGLE|D TYPE|CMOS|TSSOP|8PIN|PLASTIC

  • 92.60KB

  • 13頁(yè)

  • ETC

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74V2G74
SINGLE D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 170 MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 1
碌A(chǔ)
(MAX.) at T
A
=25擄C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
SOT23-8L
SOT323-8L
ORDER CODES
PACKAGE
SOT23-8L
SOT323-8L
T&R
74V2G70STR
74V2G70CTR
DESCRIPTION
The 74V2G74 is an advanced high-speed CMOS
SINGLE D-TYPE FLIP FLOP WITH PRESET
AND CLEAR fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
tecnology.
A signal on the D INPUT is transfered to the Q and
Q OUTPUTS during the positive going transition
of the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
December 2001
1/13

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