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74V1G79STR Datasheet

  • 74V1G79STR

  • SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP

  • 10頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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74V1G79
SINGLE POSITIVE EDGE TRIGGERED
D-TYPE FLIP-FLOP
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 180MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 1碌A(chǔ)(MAX.) at T
A
=25擄C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN) at V
CC
= 4.5V
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
IMPROVED LATCH-UP IMMUNITY
SOT23-5L
SOT323-5L
ORDER CODES
PACKAGE
SOT23-5L
SOT323-5L
T&R
74V1G79STR
74V1G79CTR
DESCRIPTION
The 74V1G79 is an advanced high-speed CMOS
SINGLE POSITIVE EDGE TRIGGERED D-TYPE
FLIP-FLOP fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. it is designed to operate from 2V to
5.5V, making this device ideal for portable
applications.
This D-Type flip-flop is controlled by a clock input
(CK). On the positive transition of the clock, the Q
output will be set to the logic state that was setup
at the D input.
Following the hold time interval, data at the D input
can be changed without affecting the level at the
output. Power down protection is provided on
inputs and 0 to 7V can be accepted on inputs with
no regard to the supply voltage. This device can
be used to interface 5V to 3V systems.
It鈥檚 available in the commercial and extended
temperature range. All inputs and output are
equipped with protection circuits against static
discharge, giving them ESD immunity and
transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
1/10

74V1G79STR 產(chǎn)品屬性

  • 1

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74V

  • 標(biāo)準(zhǔn)

  • D 型

  • 非反相

  • 1

  • 1

  • 180MHz

  • 4.5ns

  • 正邊沿

  • 8mA，8mA

  • 2 V ~ 5.5 V

  • -55°C ~ 125°C

  • 表面貼裝

  • SC-74A，SOT-753

  • Digi-Reel®

  • 497-1276-6

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