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74LVXZ161284MTX Datasheet

  • 74LVXZ161284MTX

  • BUS TRANSCEIVER|SINGLE|8-BIT|LVX-CMOS|TSSOP|48PIN|PLASTIC

  • 12頁(yè)

  • ETC

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74LVXZ161284 Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection
May 2002
Revised May 2002
74LVXZ161284
Low Voltage IEEE 161284 Translating Transceiver
with Power-Up Protection
General Description
The LVXZ161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in an
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (
鹵
14 mA) and are connected to a
separate power supply pin (V
CC-Cable
) that allows these
outputs to be driven by a higher supply voltage than
the A-side. The pull-up and pull-down series termination
resistance of these outputs on the cable side is optimized
to drive an external cable. In addition, the C inputs and the
B and Y outputs on the cable side contain internal pull-up
resistors connected to the V
CC-Cable
supply to provide
proper input termination and pull-ups for open drain output
mode.
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A
1
鈥揂
8
/B
1
鈥揃
8
transceiver
pins.
This device also has an added power-up protection feature
which forces the Y outputs (Y
9
- Y
13
) to a high state after
power-on until one of the associated inputs (A
9
- A
13
) goes
HIGH. When an associated input (A
9
- A
13
) goes HIGH, all
Y outputs (Y
9
- Y
13
) are activated.
Features
I
Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
I
Translation capability allows outputs on the cable side to
interface with 5V signals
I
All inputs have hysteresis to provide noise margin
I
B and Y output resistance optimized to drive external
cable
I
B and Y outputs in high impedance mode during power
down
I
C inputs and B, Y outputs on cable side have internal 1.4
k
鈩?/div>
pull-up resistors
I
Flow-through pin configuration allows easy interface
between the 鈥淧eripheral and Host鈥?/div>
I
Replaces the function of two (2) 74ACT1284 devices
I
Power-up protection prevents errors when the printer is
powered on but no valid signal is at the input pins
(A
9
- A
13
).
Ordering Code
Order Number
74LVXZ161284MEA
74LVXZ161284MEX
74LVXZ161284MTD
74LVXZ161284MTX
Package
Number
MS48A
MS48A
MTD48
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[RAIL]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[RAIL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
漏 2002 Fairchild Semiconductor Corporation
DS500729
www.fairchildsemi.com

74LVXZ161284MTX 產(chǎn)品屬性

  • Fairchild Semiconductor

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