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74LVXC3245TTR Datasheet

  • 74LVXC3245TTR

  • BUS TRANSCEIVER|SINGLE|8-BIT|LVX-CMOS|TSSOP|24PIN|PLASTIC

  • 12頁

  • ETC

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74LVXC3245
OCTAL DUAL SUPPLY BUS TRANSCEIVER
s
s
s
s
s
s
s
HIGH SPEED :
t
PD
= 8ns (MAX.) at T
A
=25擄C
V
CCA
= 3.3V, V
CCB
= 5.0V
LOW POWER DISSIPATION:
I
CCA
= I
CCB
= 5碌A(chǔ)(MAX.) at T
A
=25擄C
LOW NOISE: V
OLP
=0.3V (TYP.) at
V
CCA
=3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CCA
(OPR) =2.7V to 3.6V (1.2V Data Retention)
V
CCB
(OPR) =2.7V to 5.5V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES C3245
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVXC3245M
T&R
74LVXC3245MTR
74LVXC3245TTR
DESCRIPTION
The 74LVXC3245 is a dual supply 8 bit
configurable low voltage CMOS OCTAL BUS
TRANSCEIVER fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. Designed for use as an interface
between a 3.3V bus and a 3.3V to 5V bus in a
mixed 3.3V/5V supply systems, it achieves high
speed operation while maintaining the CMOS low
power dissipation.
PIN CONNECTION AND IEC LOGIC SYMBOLS
This IC is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the buses are effectively
isolated.
The A-port interfaces with the 3V bus, the B-port
with the 5V bus.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
July 2001
1/12

74LVXC3245TTR 產(chǎn)品屬性

  • 1

  • 集成電路 (IC)

  • 邏輯 - 變換器

  • 74LVXC

  • 變換器

  • 8

  • 邏輯

  • 邏輯

  • -

  • 8

  • 1

  • 無/無

  • 7.5ns

  • 2.7 V ~ 3.6 V，4.5 V ~ 5.5 V

  • -55°C ~ 125°C

  • 24-TSSOP（0.173"，4.40mm 寬）

  • 24-TSSOP

  • Digi-Reel®

  • 497-7725-6

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