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t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
POWER DOWN PROTECTION ON INPUTS
SOP
ORDER CODES
PACKAGE
SOP
TSSOP
T UBE
74LVX74M
TSSOP
T& R
74LVX74MTR
74LVX74TTR
DESCRIPTION
The 74LVX74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 2000
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