74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
May 1993
Revised February 2005
74LVX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop
General Description
The LVX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is
locked out and information present will not be transferred to
the outputs until the next rising edge of the Clock Pulse
input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
s
Input voltage level translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX74M
74LVX74SJ
74LVX74MTC
74LVX74MTCX_NL
(Note 1)
Package
Number
M14A
M14D
MTC14
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
鈥淿NL鈥?indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names
D
1
, D
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
1
, Q
2
, Q
2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
漏 2005 Fairchild Semiconductor Corporation
DS011606
www.fairchildsemi.com