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74LVX573SJX Datasheet

  • 74LVX573SJX

  • Low Voltage Octal Latch with 3-STATE Outputs

  • 7頁(yè)

  • FAIRCHILD

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74LVX573 Low Voltage Octal Latch with 3-STATE Outputs
June 1993
Revised April 2005
74LVX573
Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVX573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output
Enable (OE) inputs. The LVX573 is functionally identical to
the LVX373 but with inputs and outputs on opposite sides
of the package. The inputs tolerate up to 7V allowing inter-
face of 5V systems to 3V systems.
Features
s
Input voltage translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX573M
74LVX573SJ
74LVX573MTC
Package Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
鈥揇
7
LE
OE
O
0
鈥揙
7
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Description
漏 2005 Fairchild Semiconductor Corporation
DS011616
www.fairchildsemi.com

74LVX573SJX 產(chǎn)品屬性

  • 2,000

  • 集成電路 (IC)

  • 邏輯 - 鎖銷

  • 74LVX

  • D 型透明鎖存器

  • 8:8

  • 三態(tài)

  • 2 V ~ 3.6 V

  • 1

  • 5.9ns

  • 4mA，4mA

  • -40°C ~ 85°C

  • 表面貼裝

  • 20-SOIC（0.209"，5.30mm 寬）

  • 20-SOIC

  • 帶卷 (TR)

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