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74LVX4245MTR Datasheet

  • 74LVX4245MTR

  • OCTAL DUAL SUPPLY BUS TRANSCEIVER

  • 13頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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74LVX4245
OCTAL DUAL SUPPLY BUS TRANSCEIVER
s
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 8.5 ns (MAX.) at
V
CCA
=5.0V V
CCB
= 3.3V
LOW POWER DISSIPATION:
I
CCA
= I
CCB
=5碌A(chǔ)(MAX.) at T
A
=25擄C
LOW NOISE: V
OLP
=0.3V (TYP.) at
V
CCA
=5.5V V
CCB
=3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CCA
(OPR) = 4.5V to 5.5V (1.2V Data Retention)
V
CCB
(OPR) = 2.7V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 4245
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVX4245MTR
74LVX4245TTR
DESCRIPTION
The 74LVX4245 is a dual supply low voltage
CMOS OCTAL BUS TRANSCEIVER fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology. Designed for use
as an interface between a 5V bus and a 3.3V bus
in a mixed 5V/3.3V supply systems, it achieves
high speed operation while maintaining the CMOS
low power dissipation.
This IC is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the buses are effectively
isolated.
The A-port interfaces with the 5V bus, the B-port
with the 3.3V bus.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
Figure 1: Pin Connection And IEC Logic Symbols
August 2004
Rev. 6
1/13

74LVX4245MTR 產(chǎn)品屬性

  • 74LVX4245 View All Specifications

  • 1

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器

  • 74LVX

  • 收發(fā)器，非反相

  • 1

  • 8

  • 12mA，12mA; 24mA，24mA

  • 2.7 V ~ 3.6 V，4.5 V ~ 5.5 V

  • -55°C ~ 125°C

  • 表面貼裝

  • 24-SOIC（0.295"，7.50mm 寬）

  • 24-SOP

  • Digi-Reel®

  • 497-1091-6

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