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74LVX240SJ Datasheet

  • 74LVX240SJ

  • Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

  • 5頁

  • FAIRCHILD

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74LVX240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
May 1993
Revised March 1999
74LVX240
Low Voltage Octal Buffer/Line Driver with
3-STATE Outputs
General Description
The LVX240 is an octal inverting buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver which
provides improved PC board density. The inputs tolerate
up to 7V allowing interface of 5V systems to 3V systems.
Features
s
Input voltage translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX240M
74LVX240SJ
74LVX240MTC
Package Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-130, 0.300鈥?Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
IEEE/IEC
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
鈥揑
7
O
0
鈥揙
7
Description
3-STATE Output Enable Inputs
Inputs
Outputs
Truth Tables
Inputs
OE
1
I
n
L
H
X
Inputs
OE
2
L
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Outputs
(Pins 12, 14, 16, 18)
H
L
Z
Outputs
(Pins 3, 5, 7, 9)
I
n
L
H
X
H
L
Z
Connection Diagram
L
L
H
漏 1999 Fairchild Semiconductor Corporation
DS011609.prf
www.fairchildsemi.com

74LVX240SJ 產(chǎn)品屬性

  • 38

  • 集成電路 (IC)

  • 邏輯 - 柵極和逆變器

  • 74LVX

  • 逆變器，緩沖器

  • 2

  • 4

  • 三態(tài)

  • 2 V ~ 3.6 V

  • 4µA

  • 4mA，4mA

  • 0.5 V ~ 0.8 V

  • 1.5 V ~ 2.4 V

  • 9.7ns @ 3.3V，50pF

  • -40°C ~ 85°C

  • 表面貼裝

  • 20-SOP

  • 20-SOIC（0.209"，5.30mm 寬）

  • 管件

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