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t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 20
IMPROVED LATCH-UP IMMUNITY
POWER DOWN PROTECTION ON INPUTS
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVX20M
T&R
74LVX20MTR
74LVX20TTR
DESCRIPTION
The 74LVX20 is a low voltage CMOS DUAL
4-INPUT NAND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
PIN CONNECTION AND IEC LOGIC SYMBOLS
The internal circuit is composed of 3 stages
including buffer output, which provides high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
July 2001
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